CPLD课程设计代码.doc

附：程序代码
注：译码器，分频，点阵，流水灯，步进电机五部分为源代码的功能拓展，带下划线部分为修改或添加的代码。
交通灯，多路选择器为编写设计代码。

1、译码器：
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY decoder3_8 IS
PORT(
A,B,C: IN STD_LOGIC;
Y :OUT STD_LOGIC_VECTOR(7 DOWNTO 0); --段选输出
en :OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); --位选输出
END decoder3_8;
ARCHITECTURE fun OF decoder3_8 IS
SIGNAL indata: STD_LOGIC_VECTOR(2 DOWNTO 0) ;
BEGIN
indata <=C&B&A;
encoder:
PROCESS(indata )
BEGIN
CASE indata IS
WHEN "000"=>Y<="01000000";en<="00000001";
WHEN "001"=>Y<="01111001";en<="00000010";
WHEN "010"=>Y<="00100100";en<="00000100";
WHEN "011"=>Y<="00110000";en<="00001000";
WHEN "100"=>Y<="00011001";en<="00010000";
WHEN "101"=>Y<="00010010";en<="00100000";
WHEN "110"=>Y<="00000010";en<="01000000";
WHEN "111"=>Y<="01111000";en<="10000000";
WHEN OTHERS=>Y<="11111111";en<="00000000";
END CASE;
END PROCESS encoder;
END fun;

2、分频：
library ieee;
use ieee.std_logic_1164.all;
entity div_f is
port(clk :in std_logic;
miao_out :out std_logic;
f_miao_out:out std_logic;
fourhz :out std_logic; -- 4Hz 输出
halfhz :out std_logic; --0.5Hz输出
en :out std_logic);
end div_f;
architecture miao of div_f is
begin
en<='1';
p1:process(clk)
variable cnt:integer range 0 to 3999999;
variable ff:std_logic;
begin
if clk'event and clk='1' then
if cnt<3999999 then
cnt:=cnt+1;
else
cnt:=0;
ff:=not ff;
end if;
end if;
miao_out<=ff;
end process p1;
p2:process(clk)
variable cnn:integer range 0 to 1999999;
variable dd:std_logic;
begin
if clk'event and clk='1' then
if cnn<1999999 then
cnn:=cnn+1;
else
cnn:=0;
dd:=not dd;
end if;
end if;
f_miao_out<=dd;
end process p2;
------------p3：4Hz生成部分--------------
p3:process(clk)
variable cnt0:integer range 0 to 999999;
variable aa:std_logic;
begin
if clk'event and clk='1' then
if cnt0<999999 then
cnt0:=cnt0+1;
else
cnt0:=0;
aa:=not aa;
end if;
end if;
fourhz<=aa;
end process p3;
--------p4：0.5Hz生成部分--
p4:process(clk)
variable cnn0:integer range 0 to 7999999;
variable bb:std_logic;
begin
if clk'event and clk='1' then
if cnn0<7999999 then
cnn0:=cnn0+1;
else
cnn0:=0;
bb:=not bb;
end if;
end if;
halfhz<=bb;
end process p4;
end miao;

3、 点阵
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY dianzhen IS
PORT(clk:IN STD_LOGIC;
l : out STD_LOGIC_VECTOR(7 downto 0);
b : out STD_LOGIC_VECTOR(7 downto 0)
);
END dianzhen;
ARCHITECTURE led OF dianzhen IS
signal clk_1k:std_logic;
signal clk_1h:std_logic;
signal p,c:integer range 0 to 7;
BEGIN
-------------与源代码分频方式不同，效果相同-----------
process(clk)
variable cnt0:integer range 0 to 24676;
begin
if clk'event and clk='1'then
if cnt0=24676 then
cnt0:=0;
clk_1k<=not clk_1k;
else
cnt0:=cnt0+1;
end if;
end if;
end process;

process(p,clk_1k)
FUNCTION word(bcd8421:INTEGER RANGE 0 TO 7)RETURN
STD_LOGIC_VECTOR IS
VARIABLE smg7:STD_LOGIC_VECTOR(7 DOWNTO 0);
BEGIN
CASE bcd8421 IS
--------实现汉字“中”的编码--------
WHEN 0=>smg7:=X"00";
WHEN 1=>smg7:=X"1C";
WHEN 2=>smg7:=X"14";
WHEN 3=>smg7:=X"FF";
WHEN 4=>smg7:X"14";
WHEN 5=>smg7:=X"1C";
WHEN 6=>smg7:=X"00";
WHEN 7=>smg7:=X"00";
END CASE;
RETURN smg7;
END word;
variable cnt:integer range 0 to 63;
begin
if clk_1k'event and clk_1k='1' then
p<=p+1;
if cnt=63 then
cnt:=0;
clk_1h<=not clk_1h;
else
cnt:=cnt+1;
end if;
end if;
case p is
when 0=>b<="11111110";l<=word(c);
when 1=>b<="11111101";l<=word(c+1);
when 2=>b<="11111011";l<=word(c+2);
when 3=>b<="11110111";l<=word(c+3);
when 4=>b<="11101111";l<=word(c+4);
when 5=>b<="11011111";l<=word(c+5);
when 6=>b<="10111111";l<=word(c+6);
when 7=>b<="01111111";l<=word(c+7);
end case;
end process;
process(clk_1h)
variable cnt:integer range 0 to 7;
begin
if clk_1h'event and clk_1h='1'then
c<=c+1;
end if;
end process;
end led;

4、流水灯：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY led_lsd IS
PORT(clk:IN STD_LOGIC;
-----------
spd:in bit;---控制速度----
con:in bit;---控制方向----
r:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); ---点阵行控制
c:OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); --点阵列控制
-----------------------
END led_lsd;

ARCHITECTURE behav OF led_lsd IS
SIGNAL SLIP :STD_LOGIC_VECTOR(5 DOWNTO 0);--------
SIGNAL miao_out:STD_LOGIC;

begin
-----------------分出两个不同的频率-----------
process(clk)
variable cnt:integer range 0 to 399999;
variable ff:std_logic;
variable cnt0:integer range 0 to 1000000;
variable ff0:std_logic;
begin
if clk'event and clk='1' then
if cnt<399999 then
cnt:=cnt+1;
else
cnt:=0;
ff:=not ff;

end if;

if cnt0<1000000 then
cnt0:=cnt0+1;
else
cnt0:=0;
ff0:=not ff0;
end if;
end if;
-------速度选择--------
if(spd='1')then
miao_out<=not ff;
elsif(spd='0')then
miao_out<=not ff0;
end if;
end process;
-----------------------------------------------------
PROCESS(miao_out)
BEGIN
IF miao_out'EVENT AND miao_out='1'THEN
-----------方向选择控制--------------------------
if(con='1')then
SLIP<=SLIP+1;
elsif(con='0')then
SLIP<=SLIP-1;
end if;
--------------------------------------
END IF;
CASE SLIP IS
----------------实现LED点阵流水点灯的样式---------
WHEN"000000"=>r<="00000011";c<="11111110";
WHEN"000001"=>r<="00000011";c<="11111101";
WHEN"000010"=>r<="00000011";c<="11111011";
WHEN"000011"=>r<="00000011";c<="11110111";
WHEN"000100"=>r<="00000011";c<="11101111";
WHEN"000101"=>r<="00000011";c<="11011111";
WHEN"000110"=>r<="00000011";c<="10111111";
WHEN"000111"=>r<="00000001";c<="01111111";
WHEN"001000"=>r<="00000010";c<="00111111";
WHEN"001001"=>r<="00000100";c<="00111111";
WHEN"001010"=>r<="00001000";c<="00111111";
WHEN"001011"=>r<="00010000";c<="00111111";
WHEN"001100"=>r<="00100000";c<="00111111";
WHEN"001101"=>r<="01000000";c<="00111111";
WHEN"001110"=>r<="10000000";c<="01111111";
WHEN"001111"=>r<="11000000";c<="10111111";
WHEN"010000"=>r<="11000000";c<="11011111";
WHEN"010001"=>r<="11000000";c<="11101111";
WHEN"010010"=>r<="11000000";c<="11110111"
WHEN"010011"=>r<="11000000";c<="11111011";
WHEN"010100"=>r<="11000000";c<="11111101";
WHEN"010101"=>r<="10000000";c<="11111110";
WHEN"010110"=>r<="01000000";c<="11111100";
WHEN"010111"=>r<="00100000";c<="11111100";
WHEN"011000"=>r<="00010000";c<="11111100";
WHEN"011001"=>r<="00001000";c<="11111100";
WHEN"011010"=>r<="00000100";c<="11111100";
WHEN"011011"=>r<="00000010";c<="11111100";
WHEN"011100"=>r<="00000001";c<="11111110";
WHEN"011101"=>r<="11011011";c<="00100100";
WHEN"011110"=>r<="00000000";c<="11111111";
WHEN"011111"=>r<="11011011";c<="00100100";
WHEN"100000"=>r<="00000001";c<="11111100";
WHEN"100001"=>r<="00000010";c<="11111100";
WHEN"100010"=>r<="00000100";c<="11111100";
WHEN"100011"=>r<="00001000";c<="11111100";
WHEN"100100"=>r<="00010000";c<="11111100";
WHEN"100101"=>r<="00100000";c<="11111100";
WHEN"100110"=>r<="01000000";c<="11111100";
WHEN"100111"=>r<="10000000";c<="11111110";
WHEN"101000"=>r<="11000000";c<="11111101";
WHEN"101001"=>r<="11000000";c<="11111011";
WHEN"101010"=>r<="11000000";c<="11110111";
WHEN"101011"=>r<="11000000";c<="11101111";
WHEN"101100"=>r<="11000000";c<="11011111";
WHEN"101101"=>r<="11000000";c<="10111111";
WHEN"101110"=>r<="10000000";c<="01111111";
WHEN"101111"=>r<="01000000";c<="00111111";
WHEN"110000"=>r<="00100000";c<="00111111";
WHEN"110001"=>r<="00010000";c<="00111111";
WHEN"110010"=>r<="00001000";c<="00111111";
WHEN"110011"=>r<="00000100";c<="00111111";
WHEN"110100"=>r<="00000010";c<="00111111";
WHEN"110101"=>r<="00000001";c<="01111111";
WHEN"110110"=>r<="00000011";c<="10111111";
WHEN"110111"=>r<="00000011";c<="11011111";
WHEN"111000"=>r<="00000011";c<="11101111";
WHEN"111001"=>r<="00000011";c<="11110111";
WHEN"111010"=>r<="00000011";c<="11111011";
WHEN"111011"=>r<="00000011";c<="11111101";
WHEN"111100"=>r<="00000011";c<="11111101";
WHEN"111101"=>r<="11100111";c<="00011000";
WHEN"111110"=>r<="00000000";c<="11111111";
WHEN"111111"=>r<="11100111";c<="00011000";
-----------------------------------------
END CASE;
END PROCESS;
END behav;

5、 步进电机：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY state_machine IS
PORT (
clk :IN std_logic;
rst :IN std_logic;
spd :in bit;---速度控制---
con :in bit;---方向控制------
c :OUT std_logic_vector(3DOWNTO 0));
END state_machine;

ARCHITECTURE arch OF state_machine IS
CONSTANT state0 : std_logic_vector(2 DOWNTO 0):="000";
CONSTANT state1 : std_logic_vector(2 DOWNTO 0):="001";
CONSTANT state2 : std_logic_vector(2 DOWNTO 0):="010";
CONSTANT state3 : std_logic_vector(2 DOWNTO 0):="011";
CONSTANT state4 : std_logic_vector(2 DOWNTO 0):="100";
CONSTANT state5 : std_logic_vector(2 DOWNTO 0):="101";
CONSTANT state6 : std_logic_vector(2 DOWNTO 0):="110";
CONSTANT state7 : std_logic_vector(2 DOWNTO 0):="111";
SIGNAL state :std_logic_vector(2 DOWNTO 0);
SIGNAL KEY :std_logic_vector(2 DOWNTO 0);
BEGIN
PROCESS(clk,rst)
----实现两个分频----------
variable cnt:integer range 0 to 5999;----------
variable cnt0:integer range 0 to 9999;--------------
variable ff:std_logic;
BEGIN
IF(NOT rst='1')THEN
state<=state0;
cnt:=0;
cnt0:=0;
ELSIF(clk'EVENT AND clk='1')THEN
cnt:=cnt+1;
cnt0:=cnt0+1;-----
-------根据spd的值实现速度的选择-----------------------
if(spd='1')then
IF(cnt=5999)THEN
CASE state IS
WHEN state0=>
state<=state1;
WHEN state1=>
state<=state2;
WHEN state2=>
state<=state3;
WHEN state3=>
state<=state4;
WHEN state4=>
state<=state5;
WHEN state5=>
state<=state6;
WHEN state6=>
state<=state7;
WHEN state7=>
state<=state0;
END CASE;
END IF;
elsif(spd='0')then
IF(cnt0=9999)THEN
CASE state IS
WHEN state0=>
state<=state1;
WHEN state1=>
state<=state2;
WHEN state2=>
state<=state3;
WHEN state3=>
state<=state4;
WHEN state4=>
state<=state5;
WHEN state5=>
state<=state6;
WHEN state6=>
state<=state7;
WHEN state7=>
state<=state0;
END CASE;
END IF;
end if;
--------------
END IF;
END PROCESS;

PROCESS(state)
BEGIN
-----根据con的值实现转向控制--------------
if(con='1')then
CASE state IS
WHEN state0=>
c<="1001";
WHEN state1=>
c<="0001";
WHEN state2=>
c<="0011";
WHEN state3=>
c<="0010";
WHEN state4=>
c<="0110";
WHEN state5=>
c<="0100";
WHEN state6=>
c<="1100";
WHEN state7=>
c<="1000";
WHEN OTHERS=>
NULL;
END CASE;
elsif(con='0')then
CASE state IS
WHEN state0=>
c<="1000";
WHEN state1=>
c<="1100";
WHEN state2=>
c<="0100";
WHEN state3=>
c<="0110";
WHEN state4=>
c<="0010";
WHEN state5=>
c<="0011";
WHEN state6=>
c<="0001";
WHEN state7=>
c<="1001";
WHEN OTHERS=>
NULL;
END CASE;
end if;
--------------------------
END PROCESS;
END arch;

6、 多路选择器（四选一）：
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity selc is
port( a,b,c,d:in bit;--四路信号--
s:in std_logic_vector( 1 downto 0 );---选择信号---
data:out std_logic_vector( 7 downto 0 );---数码管段选
en:out std_logic_vector( 3 downto 0 ));---------位选---
end selc;
architecture chose of selc is
signal s0:bit;
begin
process(a,b,c,d,s)
begin
if(s="00")then
s0<=d;
case s0 is
when '1'=>data<="11111001";en<="0001";
when '0'=>data<="11000000";en<="0001";
end case;
elsif(s="01")then
s0<=c;
case s0 is
when '1'=>data<="11111001";en<="0010";
when '0'=>data<="11000000";en<="0010";
end case;
elsif(s="10")then
s0<=b;
case s0 is
when '1'=>data<="11111001";en<="0100";
when '0'=>data<="11000000";en<="0100";
end case;
elsif(s="11")then
s0<=a;
case s0 is
when '1'=>data<="11111001";en<="1000";
when '0'=>data<="11000000";en<="1000";
end case;
end if;
end process;
end chose;

7、 交通灯：
顶层文件（交通灯总模块）：
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity jiaotongdeng is
port(clk1:in std_logic;
rst:in std_logic;
con1:in std_logic;---紧急控制，实现全红灯--
segout2:out std_logic_vector(7 downto 0);---段选
led_sel1:out std_logic_vector(7 downto 0);---位选
r1,y1,g1,ryg10:out std_logic;------led红黄绿
ryg20,ryg30,ryg40:out std_logic);----灯控制
end jiaotongdeng;
architecture behavioral of jiaotongdeng is

component div_f
port
(clk:in std_logic;
rst:in std_logic;
clkout:out std_logic);
end component;

component controller
port (Clock:in std_logic;
con:in std_logic;
CountNum:in integer range 0 to 22;
NumA:out integer range 0 to 22;
r,y,g,ryg1:out std_logic;
ryg2,ryg3,ryg4:out std_logic);
end component;

component counter
port(clock:in std_logic;
con:in std_logic;
countnum:buffer integer range 0 to 22);
end component;

component fenwei
port(Numin:integer range 0 to 22;
NumA,NumB:out integer range 0 to 9);
end component;

component scan
port(clk:in std_logic;
NumA,NumB:in integer range 0 to 9;
segout1:out std_logic_vector(7 downto 0);
led_sel:out std_logic_vector(7 downto 0));
end component;
signal b,rst1:std_logic;
signal c:integer range 0 to 22;
signal d:integer range 0 to 22;
signal e,f:integer range 0 to 9;
begin
u1:div_f port map(clk=>clk1,rst=>rst,clkout=>b);
u2:counter port map(clock=>b,con=>con1,countnum=>c);
u3:controller
port map(Clock=>b,con=>con1,CountNum=>c,NumA=>d,r=>r1,y=>y1,
g=>g1,ryg1=>ryg10,ryg2=>ryg20,ryg3=>ryg30,ryg4=>ryg40);
u4:fenwei port map(Numin=>d,NumA=>e,NumB=>f);
u5:scan
port map(clk=>clk1,NumA=>e,NumB=>f,segout1=>segout2,led_sel=>led_sel1);

end behavioral;

底层文件
分频模块：
library ieee;
use ieee.std_logic_1164.all;
entity div_f is
port(clk :in std_logic;