基于LCD显示的倒计时秒表设计.doc

作品功能如下：
1、倒计时秒表具有置数功能，在相应按键作用下，可将倒计时的初始值设置在0—9999.999范围内，计到0时自动停止。
2、秒表计时范围0—9999.999秒，精度到ms。
3、LCD实时显示秒表计时值。
4、系统时钟采用实验板上提供的50MHz时钟信号源。
5、设计成同步电路模式。
模块一:分频(1ms)参见文件夹中的cout_1ms.v)
module cout_1ms(clk,rst,clock);
input rst,clk;
output clock;
reg clock;
integer i;
always @(posedge clk or negedge rst)
begin
if(~rst) clock<=0;
else
begin
     i=i+1;
     if(i==12500)
     begin
     clock<=~clock;
     i=1;
     end
end
end
endmodule
模块二:置数按键控制(参见文件夹中的ce.v)
module ce(set,seth,dain,outcome1,outcome2,outcome3,outcome4,outcome5,outcome6,outcome7);
input set,seth;
input[4:1] dain;
output[4:1] outcome1=9,outcome2=9,outcome3=9,
outcome4=9,outcome5=9,outcome6=9,outcome7=9;
reg[4:1] outcome1,outcome2,outcome3,
outcome4,outcome5,outcome6,outcome7;
integer i=1,j=1;
always@(posedge set)
if(~seth)
begin
casez(i)
1:outcome1<=dain;
2:outcome2<=dain;
3:outcome3<dain;
4:outcome4<=dain;
5:outcome5<=dain;
6:outcome6<=dain;
7:outcome7<=dain;
endcase
i=i+1;
if(i==7)i=1;
end
else i=1;
endmodule
set的第一个脉冲对第七个9置数,通过拨码置数,可调范围0~9.
set的第二个脉冲对第六个9置数,通过拨码置数,可调范围0~9.
set的第三个脉冲对第五个9置数,通过拨码置数,可调范围0~9.
set的第四个脉冲对第四个9置数,通过拨码置数,可调范围0~9.
set的第五个脉冲对第三个9置数,通过拨码置数,可调范围0~9.
set的第六个脉冲对第二个9置数,通过拨码置数,可调范围0~9.
set的第七个脉冲对第一个9置数,通过拨码置数,可调范围0~9.

模块三:实现9999999~0的倒计数(参见文件夹中的counter_8gate.v)
module counter_8gate(clk,rst,seth,en,stop,data1,data2,data3,data4,data5,data6,data7,outcome1,outcome2,outcome3,outcome4,outcome5,outcome6,outcome7);
input clk,rst,en,stop,seth;
input[4:1] data1,data2,data3,data4,data5,data6,data7;
output[4:1] outcome1=9,outcome2=9,outcome3=9,outcome4=9,outcome5=9,outcome6=9,outcome7=9;
reg[4:1] outcome1,outcome2,outcome3,outcome4,outcome5,outcome6,outcome7;
integer i=1,j=1;
reg[1:0] key_reg;
wire key_en;

assign key_en=~keyreg[0] & key_reg[1];
always @(posedge clk or negedge rst)
if(~rst)
  key_reg<=2'b00;
else
  key_reg<={key_reg[0],en};

always@(posedge clk or negedge rst)
begin
if(~rst)
   begin
   outcome1=9;outcome2=9;outcome3=9;outcome4=9;
   outcome5=9;outcome6=9;outcome7=9;i=1;j=2;
   end
else if(key_en||j>1)
     begin
     outcome1=outcome1-1;
     j=2;
     if(outcome1==4'b1111)
               begin
               outcome2=outcome2-1;
               outcome1=9;
               if(outcome2==4'b1111)
                    begin
                    outcome3=outcome3-1;
                    outcome2=9;
                         if(outcome3==4'b1111)
                                begin
                                outcome4=outcome4-1;
                                outcome3=9;
                                     if(outcome4==4'b1111)
                                         begin
                                         outcome5=outcome5-1;
                                         outcome1=4;
                                              if(outcome5==4'b1111)
                                                    begin
                                                       outcome6=outcome6-1;
                                                       outcome5=9;
                                                             if(outcome6==4'b1111)
                                                                 begin
                                                                 outcome7=outcome7-1;
                                                                 outcome6=9;
                                                                     if(outcome7==4'b1111)
                                                                           outcome7=9;

                                                                  end                                                        
                                                     end
                                          end
                                  end
                         end
                   end
      end
      else if(seth)
      begin
      outcome1=data1;
      outcome2=data2;
      outcome3=data3;
      outcome4=data4;
      outcome5=data5;
      outcome6=data6;
      outcome7=data7;
      end
end
always@(negedge stop)
begin
outcome1=outcome1;outcome2=outcome2;outcome3=outcome3;outcome4=outcome4;
outcome5=outcome5;outcome6=outcome6;outcome7=outcome7;
end
endmodule

模块四:(分频,置数,倒计数整合模块)(参见文件中的counter.v)

模块五:LCD显示(参见文件夹中的LCD.v)
LCD模块大家已经和熟悉,所以不做任何分析.