数字集成电路英文课件：Chapter 2 MOS Transistors.ppt

单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,*,单击此处编辑母版标题样式,*,Chapter 2:MOS Transistors,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,2,Outline,Introduction,Structure and Operation of the MOS Transistor,Threshold voltage of the MOS transistor,First-order Current-Voltage Characteristics,Derivation of Velocity-Saturated Current Equations,Subthreshold Condition,Capacitance of the MOS transistor,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,3,2.1 Introduction,As the transistor scaling,MOS VLSI circuits make up a dominant percentage of the total market for digital ICs.,Years-,PMOS-NMOS-CMOS,The great advantage of CMOS digital circuits is that they maybe designed with low static power consumption in the steady stage condition,but it also increase in fabrication complexity and chip area compared to basic NMOS.,The contents in this chapter:,Structure and operation of the MOS transistor,Calculation of threshold voltage,Current equation,Capacitance of the MOS transistor,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,4,2.2 Structure and Operation of the MOS Transistor-1,The MOSFET(Metal Oxide Semiconductor Field Effect Transistor)is a voltage controlled device.This means that a voltage at the gate control the current flows from the drain to the source.,Four terminals:gate/G,drain/D,source/S,bulk/B(body or substrate),G:metal(early technology)or ploy-Si(heavily doped to keep its resistance low),controlled the formation of a conducting channel,D/S:heavily doped to achieve Ohmic contact within metal electrode.The structure is symmetrical,one cannot distinguish between the source and drain of an unbiased device.,B(NMOS):connected to the lowest potential,typically GND,to keep the BD/BS pn+junction reverse-biased.,Digital Integrated Circuits,5,2.2 Structure and Operation of the MOS Transistor-2,Two Simple operation modes:On and Off.,Determined by the gate voltage,In the off condition,no current flows in the device,In the on condition,electron current flows from source to drain,A voltage is applied to the gate node to set up an electric field that creates a conductive channel between source and drain regions,and current flows when a potential difference exists between two nodes.,Faculty of Materials and Energy,GDUT,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,6,2.2 Structure and Operation of the MOS Transistor-3,Important device dimension parameters:,Channel length/L:typically in the range of 350nm and 22nm,this dimension will continue to scale according to Moores law,Channel width/W:typically much larger than the minimum length,depending on the desired current handling capability,Gate oxide thickness/T,ox,:typically less than 5nm,it determines the vertical electrical field and hence the device currents,but limited by the device reliability,e.g.breakdown voltage,Junction depth/x,j,:70-150nm,to calculate the junction capacitance,Thickness of the depletion layer thickness/x,d,:to calculate the threshold voltage,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,7,2.2 Structure and Operation of the MOS Transistor-4,The silicon surface is comprised of active and field regions.,Active region:device(or transistor).It should be defined in the layout design.,Field region:it serves to isolate transistors.A thick layer of silicon dioxide over the field regions is to minimize unwanted capacitance from interconnecting metal to the body and limit the current of parasitic transistors.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,2.3 Threshold voltage of the MOS transistor-1,Definition of threshold voltage:,V,T,is defined as the applied gate voltage required to create the inversion layer charge.(The electron concentration at the surface is the same as the hole concentration in the bulk material),V,T,is defined as the applied gate voltage required to achieve the threshold inversion point.The threshold inversion point is defined as the condition when the surface potential is,s,=2,fp,for p-type semiconductor and,s,=2,fn,for n-type semiconductor.,8,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,9,2.3 Threshold voltage of the MOS transistor-2,The three main terms of threshold voltage are:,The difference in work functions between the gate material and the silicon substrate on the channel side.,The positive charge Q,ox,present in the oxide and the interface between the oxide and the bulk silicon.It contributes a negative quantity to the threshold voltage of Q,ox,/C,ox,.,The flat-band voltage:A voltage at the gate produces flat energy bands in the MOS system.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,10,2.3 Threshold voltage of the MOS transistor-3,The three main terms of threshold voltage are:,A gate voltage(-2,F,-Q,B,/C,ox,)is needed to change the surface potential to the strong inversion condition and to offset the induced depletion-layer charge Q,B,.,The threshold voltage can be calculated by:,Where:,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,11,2.3 Threshold voltage of the MOS transistor-4,As V,b,becomes more negative,more holes are attracted to the substrate connection,leaving a larger negative charge behind.,The threshold voltage is a function of the total charge in the depletion region because the gate charge must mirror Q,B,before an inversion layer is formed.Thus,as V,B,drops and Q,B,increase,V,T,also increases.This is the body effect or the back gate effect.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,12,2.3 Threshold voltage of the MOS transistor-5,For body effect to manifest itself,the bulk potential need not change;if the source voltage varies with respect to bulk potential,the same phenomenon occurs.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,13,2.3 Threshold voltage of the MOS transistor-6,Problem:A 130nm technology employs carrier concentrations in the p-well in the range of 310,17,cm,-3,.Estimate the degree of band-bending required for strong inversion at room temperature,relative to the flat-band condition.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,14,2.3 Threshold voltage of the MOS transistor-7,Problem:A P-type well in a 130nm technology has N,A,=310,17,cm,-3,.Find the limiting value of depletion-layer width and the total charge contained in the depletion region.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,15,2.3 Threshold voltage of the MOS transistor-8,Problem:Determine values of C,ox,and,if t,ox,=2.2nm and,N,A,=310,17,cm,-3,.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,16,2.3 Threshold voltage of the MOS transistor-9,Problem:Calculate the zero-bias threshold voltage for an NMOS silicon-gate transistor that has well doping N,A,=310,17,cm,-3,gate doping N,D,=10,20,cm,-3,gate oxide thickness tox=2.2nm,and 210,10,cm,-2,singly charged positive ions per unit area at the oxide silicon interface.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,17,2.3 Threshold voltage of the MOS transistor-10,The breakdown voltage and junction capacitance maybe affected by the variation of doping concentration in the gate and oxide capacitance.,The value of threshold voltage is determined by ion implanting dopant atoms into the channel region.,A p-type threshold implant(boron)will make the threshold voltage more positive.,A N-type threshold implant(phosphorus)will make the threshold voltage more negative.,Problem:Calculation of threshold voltage implant dosage.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,18,2.4 First-order Current-Voltage Characteristics-1,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,18,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,19,2.4 First-order Current-Voltage Characteristics-2,The current flows through a semiconductor bar can be described as:,Q,n,:charge density along the direction of current,V:velocity of the charge,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,20,2.4 First-order Current-Voltage Characteristics-3,The charge density can be calculated by:,C,ox,:Capacitance of gate oxide per unit area,T,ox,:thickness of gate oxide,V(y):channel potential at y,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,21,2.4 First-order Current-Voltage Characteristics-4,If V,ds,V,gs,-V,T,the device is operated in the triode region.,V,gs,-V,T,:overdrive voltage W/L:aspect ratio,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,22,2.4 First-order Current-Voltage Characteristics-5,If V,ds,2(V,gs,-V,T,),then,The MOSFET is operated as a resistor whose value is controlled by the overdrive voltage.With the condition V,ds,V,gs,-V,T,Ids becomes relatively constant and we define the device is operated in the saturation region.,Why?,The density of inversion layer charge is proportional to V,gs,-V(y)-V,T,.If channel potential V(y)approaches V,gs,-V,T,then Q,n,(y)drops to zero and the channel is pinch off.As V,ds,increase further,the point at which Q,n,equals to zero gradually moves toward the source.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,24,2.4 First-order Current-Voltage Characteristics-7,The I-V equation of MOSFET in the saturation region can be derived as:,In the long channel devices,the saturated MOSFET can be used as a current source connected between the drain and source.The current is controlled by the overdrive voltage.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,25,Design of Analog CMOS Integrated Circuits,DME,GDUT,25,2.4 First-order Current-Voltage Characteristics-8,As the device is operated in the saturation region,the actual length of the inverted channel gradually decreases as the potential difference between the gate and the drain increases.In other words,L is in fact as a function of Vds.This effect is defined as channel length modulation.,Channel length modulation is more significant in the short channel devices and can be ignored in the long channel devices.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,26,2.5,Velocity-Saturated Current Equations-1,In the long channel devices,saturation occurs when V,ds,=V,gs,-V,T,In the deep submicron devices,saturation occurs when the carriers reach velocity saturationthat is,when they reach the speed limit of the carriers in silicon.,Velocity saturation is due to the high horizontal and vertical fields.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,27,2.5 Velocity-Saturated Current Equations-2,The vertical field can be approximated as E,x,=V,GS,-V,T,/t,ox,.,For high gate voltages,a large number of mobile carriers are induced in the inversion layer near the interface.The mobility of these carriers decreases due primarily to electron scattering caused by dangling bonds at the Si-SiO,2,interface.The effect of the vertical field on mobility can be modeled as:,The vertical field(5.510,6,V/cm)is very large than the horizontal field(1.210,5,V/cm),and the effective mobility is reduced by a factor of 2 relative to the nominal mobility in the presence of low fields.(NMOS:540-270cm,2,/V-s),Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,28,2.5 Velocity-Saturated Current Equations-3,The horizontal field is given by E,y,=V,DS,/L,The horizontal field acts to push the carriers to their velocity limit and this cause early saturation.,The horizontal field acts to reduce the mobility.As E,y,goes up,the carriers continue to increase in speed.Actually their velocity saturates a limit at approximately v,sat,=10,7,cm/s.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,29,2.5 Velocity-Saturated Current Equations-4,initially,as E,y,increase,the carrier velocity also increases,the mobility is keep constant.,The field increase beyond a certain critical electrical field,E,C,the carrier velocity saturates at its limit in silicon.The horizontal fields are so high in DSM devices that they tend to saturate very quickly as V,DS,increases.,The horizontal field is given by E,y,=V,DS,/L,The horizontal field acts to push the carriers to their velocity limit and this cause early saturation.,The horizontal field acts to reduce the mobility.As E,y,goes up,the carriers continue to increase in speed.Actually their velocity saturates a limit at approximately v,sat,=10,7,cm/s.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,30,2.5 Velocity-Saturated Current Equations-5,The saturation velocity for both electrons and holes is 810,6,cm/s at T=400K.The critical field values are:,T=300K,v,sat,=10,7,cm/s,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,31,2.5 Velocity-Saturated Current Equations-6,The horizontal electric field,E,y,can be expressed as:,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,32,2.5 Velocity-Saturated Current Equations-7,Current equations for velocity-saturated devices(linear region):,?,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,33,2.5 Velocity-Saturated Current Equations-8,Current equations for velocity-saturated devices(saturation region):,For long channel devices,E,C,LV,GS,-V,T,For short channel devices,E,C,LV,GS,-V,T,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,34,2.6 Subthreshold Condition,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,35,2.7 Capacitance of the MOS transistor-1,The switching speed of MOS digital circuits is limited by the time required to charge and discharge the capacitances at internal node,which must be calculated from device dimensions and dielectric constants.,Two nonlinear or voltage dependent capacitances:,Thin oxide capacitances:C,gs,C,gd,C,gb,Junction capacitances:C,sb,C,db,Linear and voltage independent capacitance,Overlap capacitance:C,ol,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,36,2.7 Capacitance of the MOS transistor-2,The two plates of the thin oxide capacitance are defined as the gate and the channel.The dielectric material is the oxide sandwiched between these two plates.The total capacitance of the thin oxide is:,C,ox,is the capacitance per unit area of the gate dielectric.,Cg has remained constant for over 25 years.The reason is that both L and tox are scaled at the same rate.,Digital Integrated Circuits,Faculty of Materials and Energy,GDUT,37,2.7 Capacitance of the MOS transistor-3,When the device is cutoff,the channel is not existed between the drain and source.The gate-to-drain and gate-to-source capacitance is zero,that is,C,gs,=C,gd,=0.the gate-to-bulk capacitance is approximated to:C,gb,=WLCox,.,In the linear region,C,gs,and C,gd,are approximately equal to(1/2)C,g,since the channel extends from source to drain.,In the saturation region,the channel extends most of the way from source to drain,so most of the gate capacitance can be attributed to the source node,and a negligible amount t