模拟集成电路的分析与设计：Chapter 4-Differential Amplifiers.ppt

单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,Differential Amplifiers(,差分运放）,overview,Differential Amplifiers,Why differential(1),a.Higher immunity to environmental noise,Differential Amplifiers,Why differential(2),b.Reject supply noise,Differential Amplifiers,Why differential(3),c.Reduce coupled noise in transmission line,Differential Amplifiers,Why differential(4),d.Other advantages,Increase output swing from V,DD,-(V,GS,-V,TH,)to 2V,DD,-(V,GS,-V,TH,),Simpler biasing,Higher linearity,Drawback:,occupy twice area,Differential Amplifiers,D,ifferential pair(1),Problem of simple differential circuit:,If V,in,CM,is low,output will be clipped,Differential Amplifiers,D,ifferential pair(2),Solve method:,Use differential pair,Independent on V,in,CM,Differential Amplifiers,D,ifferential pair(3),Common-mode behavior:,I,SS,/2,I,SS,Back,Differential Amplifiers,D,ifferential pair(4),When 0V,cm,in,minV,DD,-R,D,I,SS,/2+V,TH,V,DD,:,M,1,and M,2,in triode region,V,cm,in,I,D1,=I,D2,|A,V,|,Differential Amplifiers,D,ifferential pair(5),Quantitative Analysis(,定量分析）,:,Assuming circuit is symmetric,M,1,and M,2,are set in saturation region.,Problem transferred to calculate the current difference I,D1,-I,D2,.Differential Amplifiers,D,ifferential pair(6),Squaring two sides and using I,D1,+I,D2,=I,SS,Squaring two sides again and using,4I,D1,I,D2,=(I,D1,+I,D2,),2,-(I,D1-,I,D2,),2,=I,SS,2,-(I,D1-,I,D2,),2,Differential Amplifiers,D,ifferential pair(7),Denote,I,D,=I,D1,-I,D2,and V,in,=V,in1,-V,in2,At equilibrium condition,V,in,=0,G,m,is maxmum:,Differential Amplifiers,D,ifferential pair(8),The condition of G,m,=0:,Differential Amplifiers,D,ifferential pair(9),If R,T1,=R,T2,and V,T1,=-V,T2,then V,P,not change,the node P can be considered as“ac ground”,and thus the differential circuit can be decomposed into two halves:,Small-signal analysis(if symmetric):,Thevenin(,戴维南）,equivalent,Differential Amplifiers,D,ifferential pair(10),Half-circuit concept:,The amplification is same as that of the simple common-source stage!,Differential Amplifiers,D,ifferential pair(11),If transistors not symmetric(g,m1,gm2,),:,g,m1,g,m2,Differential Amplifiers,D,ifferential pair(12),First consider V,in1,to V,X,(let V,in2,=0):,If I,SS,is ideal,R,SS,=,Common-gate input resistance R,S,1/g,m2,(See P.80),Common-source with degeneration output:,Differential Amplifiers,D,ifferential pair(13),Then consider V,in1,to V,Y,(Vin2,=0):,Common-gate output(p.79):,Source follower:,Differential Amplifiers,D,ifferential pair(14),Due to symmetric structure and negative sign:,Differential Amplifiers,D,ifferential pair(15),Hence:,Differential gain:,Differential Amplifiers,D,ifferential pair(16),Consider symmetry but channel-length modulation effect(,0),:,Differential Amplifiers,D,ifferential pair(17),Consider arbitrary inputs:,Decomposed into differential-mode signal(,差模信号）,and,common-mode signal,（共模信号）,.,Differential Amplifiers,D,ifferential pair(18),While common-mode signal does not affect output if circuit is ideal,differential-mode signal amplification.,Differential Amplifiers,D,ifferential pair(19),What if the circuit is non-ideal?for example:,What if the resistance of current source is finite;,What if exists mismatch?,Common-mode input will affect output signals.,How?,Differential Amplifiers,D,ifferential pair(20),If output resistance of current source is finite;,Change bias current and thus g,m,and A,V,DM,.,Detail pls.See Example 4.6,p119-120,Differential Amplifiers,D,ifferential pair(21),And more,if load R,D,are not symmetry too?,A common-mode change at the input introduces a differential component at the output!,The circuit exhibits common-mode to differential conversion!,Differential Amplifiers,D,ifferential pair(22),If R,D,symmetry,but M,1,and M,2,are not symmetry;,Differential Amplifiers,D,ifferential pair(23),Small-signal analysis:,Differential Amplifiers,D,ifferential pair(24),Now lets calculate A,DM-DM,if M,1,and M,2,are not symmetry,use the analysis method same as Fig 4.15(p.111):,+,-,1/g,m2,R,SS,R,D,V,in1,X,1/g,m2,R,D,Y,Use Thevenin equivalent to M,1:,M,1,M,2,Differential Amplifiers,D,ifferential pair(25),+,-,R,D,V,in1,X,+,-,V,in1,1/g,m1,+,-,V,in1,1/g,m1,V,T,R,SS,R,T,Use Thevenin equivalent to M,2:,M,1,+,-,R,D,V,in1,X,M,1,R,SS,Differential Amplifiers,D,ifferential pair(26),Use Thevenin equivalent to M,2:,+,-,V,T,R,T,R,D,Y,M,2,Differential Amplifiers,D,ifferential pair(27),So,:,Differential Amplifiers,D,ifferential pair(28),By symmetry,:,And hence,:,Common mode rejection ratio(共模抑制比）,:,where g,m,denotes the mean value,:,g,m,=(g,m1,+g,m2,)/2,Differential Amplifiers,D,ifferential pair with MOS loads(1),With diode connected load:,P.54,To achieve high gain,need(W/L),P,If I,D,constant,then need(V,GSP,-V,THP,),This lowering the CM level at nodes X and Y,limit the output swing.X,Y,Differential Amplifiers,D,ifferential pair with MOS loads(2),With current-source load,:,To achieve high gain,increase L,1,L,4,.,Differential Amplifiers,D,ifferential pair with MOS loads(3),With Cascode structure,small size produces large gain,with cost of increasing headroom,Differential Amplifiers,VGA and Gilbert Cell,(1),VGA,:variable-gain amplifier,V,cout,control the gain of the differential amplifier,Differential Amplifiers,VGA and Gilbert Cell,(2),Sum two of VGAs can make the gain change from negative to positive,Directly connect drain ends of M,1,M,4,and M,2,M,3,Differential Amplifiers,VGA and Gilbert Cell,(3),If all symmetry,then:,In Fig.4.36(b),V,cont1,and V,cont2,must vary I,1,and I,2,in opposite directions such that the gain of the amplifier changes monotonically(,单调地），,Fig.4.36(c)or Fig.4.36(d)can provide this function easily.,For I,1,=0,V,out,=+g,m,R,D,V,in,;,For I,2,=0,V,out,=-g,m,R,D,V,in,;,For I,1,=I,2,g,m1,=g,m2,so V,out,=0;,Differential Amplifiers,VGA and Gilbert Cell,(4),Gilbert Cell,:add M,5,and M,6,to control the gain,If V,cont,=0,V,out,=0;,If V,cont,=+|V,cont,max,|,V,out,=-g,m,R,D,V,in,;,If V,cont,=-|V,cont,max,|,V,out,=+g,m,R,D,V,in,;,V,cont,A,V,Monotonically change,Differential Amplifiers,VGA and Gilbert Cell,(5),Change the position of V,in,and V,cont,Result is same.,correction:p128“V,cont,is very positive,then only M,1,and M,2,are on”should be“.M,1,and M,3,are on”,Questions for Chap.4(1),(1).Describe advantages and drawbacks of differential signals comparing with single-ended signal.,(2).What is the problem of simple differential circuit?How to solve this problem?,(3).If all symmetry,is the small signal gain of differential pair:,Larger than,that of the common-source single stage?,Same as that of the,common-source single stage?,Smaller than that of the,common-source single stage?,(4).If there is a small mismatch between M,1,and M,2,how do the parameters of the transistors affect the common mode rejection ratio(CMRR)of a differential pair?,Questions for Chap.4(2),(5).Write the gain(A,v,)expression of a differential pair with diode connected load(Fig.1).Can we reduce(W/L),P,to achieve high gain?Any problem if we do so?,X,Y,(6).Write the gain(A,v,)expression of a differential pair with current-source load(Fig.2).How to increase its gain?,Fig.1,Fig.2,Questions for Chap.4(3),(7).Write the gain(A,v,)expression of a differential pair with cascode structure(Fig.3).What can we learn from this circuit?,Fig.3,(8).What is VGA?Explain its work principle in short(,简单描述）,?,Questions for Chap.4(4),(9).Q4.2(p129),(10).Q4.13(p130),(11).Q4.18,only calculate that of Fig.4.38(a)and(e)(p130-131),(12).Q4.19(p130-132),