超大规模集成电路设计导论(VLSI)总复习(全英).docx

VLSI复习

题型：
缩写 5题 10分
简答 12题 60分
计算 3题 30分

缩写
英文
中文
VLSI
Very large scale integration
超大规模集成
VTC
Voltage transfer characteristic
电压传输特性
PT
Pass-Transistor
传输管
TG
Transmission Gate
传输门
CPL/DPL
Differential Pass-transistor Logic
差分传输管逻辑
MS
Master-Slave
主从
ET
Edge-Triggered
边沿触发
CMOS
Complementary metal oxide semiconductor
互补型金属氧化物半导体管
NoC
On-Chip Network
片上网络
SoC
System on Chip
片上系统
IP
Intellectual Property
 专利
GA
Gate Array
门阵列
FPGA
Field-Programmable Gate Array
现场可编程门阵列
PLA
Programmable Logic Array
可编程逻辑阵列
PLD
Programmable Logic Device
可编程逻辑器件
PAL
Programmable Array Logic Device
可编程阵列逻辑器件
LUT
Look-up Table
查表
FAMOS
Floating-gate transistor(metal oxide semiconductor)
浮栅晶体管
S/DRAM
Static/Dynamic Random Access Memory
静/动态可读写存储器
RWM
Read-write memory
读写存储器
ATD
Address Transition Detection
地址翻转探测
DFT
Design-for-test
可侧性设计
DUT
Device under test
被测器件
BIST
Built in self test
内建自测试
EDA
Electronic Design Automation
电子设计自动化
TSPCR
True Single-Phase Clocked Tegister
真单相钟控寄存器

Chapter 01
1. How to evaluate performance
• Cost
• Reliability
• Speed (delay, operating frequency)
• Power dissipation
2. Regenerative property
3. Delay :

Chapter 02
1. Inverter layout

2. Photolithography process
1) Oxidation layering(氧化层)
2) Pthotoresist coating（涂光刻胶）
3) Stepper exposure（光刻机曝光）
4) Photoresist development and bake(光刻胶的显影和烘干)
5) Acid etching（酸刻蚀）
6) Spin, rinse, and dry（旋转，清洗和干燥）
7) Various process steps：
Ion implantation（离子注入）
Plasma etching（等离子刻蚀）
Metal deposition（金属沉淀）
8) Photoresist removal( or ashing) 去除光刻胶（即“沙洗”）

Chapter 03
1. Linear/ Saturation mode

2. Long channel vs short channel

3. Capacitances= structure capacitances+channel capacitances+MOS diffusion capacitances
4. Resistance=MOS sructure resistance+source and drain resistance+cantact resistance+wiring resistance
With silicidation R方块ˆ is reduced to the range 1 to 4 Ω/方块（source and drain resistance）

Chapter 04
1. Cwire = Cpp +  Cfringe + Cinterwire
2. Dealing with resistance:
1) Use better interconnect materials
2) More interconnect layers
3. RC Mode
• Lumped RC model
– total wire resistance is lumped into a single R and total capacitance into a single C
– good for short wires; pessimistic and inaccurate for long wires
• Distributed RC model
– circuit parasitics are distributed along the length, L, of the wire
4. Delay

Delay of a wire is a quadratic function of its length, L
The delay is 1/2 of that predicted (by the lumped model)
5. Reflection coefficient
【画传输图（or 波形），计算题】

Chapter 05
1. VM∝(W/L)p/(W/L)n
Increasing the width of the PMOS moves VM towards VDD, ‰
Increasing the width of the NMOS moves VM towards GND.
2. Delay

3. Power in CMOS
1. Dynamic power consumption: charging and discharging capacitors;
Not a function of transistor sizes;
Need to reduce CL,Vdd,and f to reduce power.
2. Short circuit currents: short circuit path supply rails during switching;
Keep the input and output rise/fall times the same;
If Vdd<Vtn+|Vtp|,then short-circuit power can be eliminated.
3. Leakage: leaking diodes and transistors
4. Technology scaling models
Full scaling
Fixed voltage scaling
General scaling

Chapter 06
1. Static CMOS- output connected to either Vdd or GND via a low-resistance path
n High noise margins
n Low output impedance, high input impedance
n No steady state path between Vdd and GND
n Delay is a function of load capacitance and transistor resistance
Dynamic CMOS--relies on temporary storage of signal values on capacitance of high-impedance circuit nodes.
n Simpler, faster gates
n Increased sensitivity to noise
2. Static vs dynamic circuit
n In static circuit at every point in time (except when switching) the output is connected to either GND or VDD via a low resistance path.
--fan-in of N requires 2N devices
n Dynamic circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes
--requires only N+2 transistors
--takes a sequence of precharge and conditional evaluation phases to realize logic functions.
l conditions on output
1) once the optput of a dynamic gate is discharged, it cannot be charged again until the next precharge opreation.
2) Inputs to the gate can make at most one transition during evaluation.
3) Output can be in the high impedance state during and after evaluation(PDN off), state is stored in CL.
l Properties of Dynamic Gates
1) Logic function is implemented by the PDN only
– number of transistors is N + 2 (versus 2N for static complementary CMOS)
– should be smaller in area than static complementary CMOS
2) Full swing outputs (VOL = GND and VOH = VDD)
3) Nonratioed
--sizing of the devices is not important for proper functioning  (only for performance)
4) Faster switching speeds
5) Power dissipation should be better
- consumes only dynamic power –no short circuit power consumption since the pull
- up path is not on when evaluating
- lower CL--both Cint(since there are fewer transistors connected to the drain output) and Cext (since there the output load is one per connected gate, not two)
- by construction can have at most one transition per cycle – no glitching
6) Needs a percharge clock
3. Combinational vs Sequential logic
4. Why PMOS in PUN and NMOS in PDN?
Threshold drops

5. Ratioed logic: Pseudo-NMOSàSmall area and load, but static power dissipation

Chapter 07
1. Latch vs Register
n Latch: level sensitive----
As for positive: passes inputs to Q when the clock is high----transparent mode;
When clock is low----hold mode
n Flip-flop: edge sensitive
2. Bistable circuit:
The cross coupling of two inverters results in a bistablecircuit (a circuit with two stable states)

n Have to be able to change the stored value by making A (or B) temporarily unstable by increasing the loop gain to a value larger than 1
Done by applying a trigger pulse at Vi1 or Vi2
the width of the trigger pulse need be only a little larger than the total propagation delay around the loop circuit (twice the delay of an inverter)
n Two approaches used
1. cutting the feedback loop (mux based latch)
2. overpowering the feedback loop (as used in SRAMs)
3. MS ET timing properties

n Set-up time: time before rising edge of clk that D must be valid
n Propagation delay: time for QM to reach Q
n Hold time: time D must be stable after rising edge of clk
4. Pipelining
5. Schmitt Trigger
(rise—P; fall—N)

Chapter 09
1. Cross Talk: An unwanted coupling from a neighboring signal wire to a network node introduces an interference that is generally called cross talk.
2. Dealing with Capacitive Cross Talk
• Avoid floating nodes
• Protect sensitive nodes
• Make rise and fall times as large as possible
• Differential signaling
• Do not run wires together for a long distance
• Use shielding wires
• Use shielding layers
3. Cross Talk and Performance: when neighboring lines switch in opposite direction of victim line, delay increases.
4. Impact of resistance is commonly seen in power supply distribution:
– IR drop
– Voltage variations

Chapter 10
1. Clock Nonidealities:
n Clock skew: Spatial variation in temporally equivalent clock edges;
n Clock jitter: Temporal variations in consecutive edges of the clock signal
n Variation of the pulse width
2. Clock Uncertainties----Source of clock uncertainty
（图形填空）
（重点）简答题：
• Clock‐Signal Generation (1)
• Manufacturing Device Variations (2)
• Interconnect Variations (3)
• Environmental Variations (4 and 5)
• Capacitive Coupling (6 and 7)
3. Impact of Positive/Negative Clock Skew and Clock jitter (重点)
1. Positive clock skew:Clock and data flow in the same direction

2. Negative clock skew: Clock and data flow in opposite directions

3. Jitter cause T to vary on a cycle-by-cycle basis

Combined impact of skew and jitter:
Constraints on the minimum clock period (positive)

4.To reduce dynamic power, the clock network must support clock gating (shutting down(disabling the clock ) units)
5. Clock distribution techniques
--Balanced paths(H-tree network, matched RC trees)
--Clock grids: minimize absolute delay
6.Matched RC trees, represents a floor plan that distributes the clock signal so that the interconnections carrying the clock signals to the functional subblocks are of equal length.
7. 彩图9：The unbalanced load creates a large skew, by careful tuning of the wire width, the load is balanced, minimizing the skew.
8. Dealing with Clock Skew and Jitter
•To minimize skew, balance clock paths using H-treeor matched-tree clock distribution structures.
• If possible, route data and clock in opposite directions; 
eliminates races at the cost of performance.
• The use of gated clocks to help with dynamic power consumption make jitter worse.
• Shield clock wires (route power lines –VDD or GND –next to clock lines) to minimize/eliminate 
coupling with neighboring signal nets.
• Use dummy fills to reduce skew by reducing variations in interconnect capacitances dueto
interlayer dielectric thickness variations.
• Beware of temperature and supply rail variations and their effects on skew and jitter.  
• Power supply noise fundamentally limits the performance of clock networks.

Chapter 11
1. Full adder
(P=A+B)
2. Static vs dynamic Manchester Carry Chain

Static dynamic
3. Square Root Carry Select Adder (PPT 24)
4. Wallace‐Tree Multiplier(PPT 32)
5. Logarithmic Shifter

Chapter 12
1. Semiconductor Memory Classification

2. Bit line & word line
3. Memory Timing(DRAM vs SRAM)
DRAM: Multiplexde Addressing
SRAM: Self-timed Address Switching/Changing
4. MOS OR ROM

0
1
0
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0
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1
0
0
0
0

MOS NOR ROM

1
0
1
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0
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1
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1
1

5. SRAM vs DRAM

STATIC (SRAM)
DYNAMIC (DRAM)
Data stored as long as supply is applied
Large (6 transistors/cell)
Fast
Differential
Periodic refresh required
Small (1-3 transistors/cell)
Slower
Single Ended

6. DRAM Timing

7. SRAM ATD(Address Transition Detection)

Chapter 13
1. Two Important Test Properties
• Controllability ‐ measures the ease of bringing a 
node to a given condition using only the input pins
• Observability ‐ measures the ease of observing the 
value of a node at the output pins
2. Test Approaches
• Ad‐hoc testing
• Scan based test
• Self test
3. Scan Register

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