(内存基本知识)DRAM工作原理.ppt

Ramaxel Technology Limited,Ramaxel Technology Limited,Confidential,DRAM,工作原理,DRAM,工作原理,Dynamic Random Access Memory,Each cell is a capacitor+a transistor,Very small size,SRAM uses six transistors per cell,Divided into banks,rows&columns,Each bank can be independently controlled,DRAM,Main Memory,Everything that happens in the computer is resident in main memory,Capacity:around 100,Mbyte,to 100,Gbyte,Random access,Typical access time is 10-100 nanoseconds,Why DRAM for Main Memory?,Cost effective(small chip area than SRAM),High Speed(than HDD,flash),High Density(,Gbyte,),Mass Production,Main memory,Notation:K,M,G,In standard scientific nomenclature,the metric,modifiers K,M,and G to refer to factors of 1,000,1,000,000 and 1,000,000,000 respectively.,Computer engineers have adopted K as the,symbol for a factor of 1,024(210),K:1,024(210),M:1,048,576(220),G:1,073,741,824(230),DRAM density,256M-bit,512M-bit,DRAM Density,What is a DRAM?,DRAM stands for Dynamic Random Access Memory.,Random access refers to the ability to access any of,the information within the DRAM in random order.,Dynamic refers to temporary or transient data storage.,Data stored in dynamic memories naturally decays over time.,Therefore,DRAM need periodic refresh operation to prevent data loss.,Memory:DRAM position,Semiconductor memory device,ROM:Non volatile,Mask ROM,EPROM,EEPROM,Flash,NAND:low speed,high density,NOR:high speed,low density,RAM:Volatile,DRAM:Dynamic Random Access Memory,SRAM:Static Random Access Memory,Pseudo SRAM,DRAM Trend:Future,High Speed,-DDR(333MHz500MHz),DDR2(533800Mbps),DDR3(8001600Mbps),-Skew-delay minimized circuit/logic:post-charge logic,wave-pipelining,-New Architecture:multi-bank structure,high speed Interface,Low Power,-5.5V=3.3V,(sdr,)=2.5V,(ddr,)=1.8V(ddr2)=1.5v(ddr3)=1.2v?,-Small voltage swing I/O interface:LVTTL to SSTL,open drain,-Low Power DRAM(PASR,TCSR,DPD),High Density,-Memory density:32MB=64MB=.1GB=2GB=4GB,-application expansion:mobile,memory DB for shock(than HDD),-Process shrink:145nm(03)=120nm(04)=100nm=90nm=80nm,Other Trends,-Cost Effectiveness,Technical Compatibility,Stability,Environment.Reliability,Static RAM,SRAM,Basic storage element is a 4 or 6 transistor circuit which will hold a 1 or 0 as long as the system continues to receive power,No need for a periodic refreshing signal or a clock,Used in system cache,Fastest memory,but expensive,SRAM Element,Enable Line,/Bit Line,Bit Line,Dynamic RAM,DRAM,Denser type of memory,Made up of one-transistor(1-T)memory cell which consists of a single access transistor and a capacitor,Cheaper than SRAM,Used in main memory,More complicated addressing scheme,DRAM Cell,Word Line,Bit Line,Refresh in,DRAMs,Capacitor leaks over time,the DRAM must be“REFRESHED”.,DRAM Cell,Word Line,Bit Line,Capacitance Leakage,SRAM vs.DRAM,DRAM Lead Frame and Wire bonding,DRAM Architecture,SDRAM has the multi bank architecture.,Conventional DRAM was product that have single bank architecture.,The bank is independent active.,memory array have independent internal data bus that have same width as external data bus.,Every bank can be activating with interleaving manner.,Another bank can be activated while 1st bank being accessed.(Burst read or write),Multi Bank Architecture,DRAM Multi Bank Architecture,DRAM Single Bank Architecture,DRAM Block Diagram(1),DRAM Block Diagram(2),DRAM Core Architecture,DRAM Address,DRAM Core Architecture,16bit DRAM Core,DRAM Data Path,DRAM 1T-1C structure,RAS:row address strobe,CAS:column address strobe,WE:write enable,Address:code to select memory cell location,DQ(I/O):bidirectional channel to transfer and receive data,DRAM cell:storage element to store binary data bit,Refresh:the action to keep data from leakage,Active:sense data from DRAM cell,Pre charge:standby state,DRAM Key word,DRAM cell array consist of so many cells.,One transistor&One capacitor,Small sense amplifier,Low input gain from charge sharing,CS:Small storage capacitor:25fF,CBL:Large parasitic capacitor:over 100fF,Vc,:Storage voltage,VCP:half,Vc,for plate bias,VBLP:half,Vc,for BL pre charge bias,(initial bias),DRAM Cell,DRAM Array Overview,Simplified Example,Activating a Row,Activating a Row,Must be done before a read or write,Just latch the row address and turn on a single,wordline,Writing,Writing,A row must be active,Select the column address,Drive the data through the column,mux,Stores the charge on a single capacitor,Reading,Reading,A row must be active,Select the column address,The value in the sense-amplifier is driven back out,The Sense-Amplifier,Sense-Amplifier,A pair of cross-coupled inverters,Basically an SRAM element,Weaker than the column,mux,Write data will“outmuscle”the sense-amplifier,Keeps the data at full level,Precharge,Precharge,Inactive state(no,wordlines,active),Precharge,control line high,Ties the two sides of the sense-amp together,This makes the,bitlines,stay at VDD/2,Only stable as long as the,precharge,control line is high,otherwise this is unstable!,No capacitors connected,Activation Revisited,Activation,Turn off the,precharge,control line,Makes the sense-amp unstable,it wants to go to either 0 or 1 instead of staying at VDD/2,A very very very short time later,turn on the,wordline,of the row to be activated.,Couples the capacitor onto the,bitlines,This“tips”the,bitlines,to hold the stored value.,The sense-amp amplifies the capacitor back to full value.(hence the name!),DRAM Refresh,Because the stored memory value is stored on a capacitor(that has resistive leakage),the memory is constantly“forgetting”its contents.,Eventually,the charge on the capacitor wont be enough to tip the sense-amp in the right direction.,But,activating a row restores the cells on that row to their full value.,There is an explicit refresh command that just activates and immediately deactivates a row.,The DRAM has an internal counter that contains the next row to be refreshed and increments every time a refresh command is issued.,DRAM Refresh,Data Retention Time,DRAM Cell consists of capacitance which has leakage as time,Retention time is period for maintaining its data especially 1 data,Usually,DRAM Cell refresh period is 64ms,Refresh Timing,tREF,:Real cell retention time(Device characteristic),ex)90ms(Hot),tRFC,:Refresh command operating time,ex)75ns,Refresh Spec.,Burst Refresh:64ms,Distribute refresh,-128Mb device(12 Row address):64ms/4K=15.6us,-256Mb device(13 Row address):64ms/8K=7.8us,AUTO Refresh,When this command is input from the IDLE state,the synchronous DRAM starts,autorefresh,operation.During the auto-refresh operation,refresh address and bank select address are generated inside the Synchronous DRAM.For every auto-refresh cycle,the internal address counter is updated.Accordingly,8192times are required to refresh the entire memory.,Before executing the auto-refresh command,all the bank must be IDLE state.In addition,since the,Precharge,for all bank is automatically performed after auto-refresh,no,Precharge,command is required after auto-refresh.,Self Refresh,Self-Refresh EntrySELF:When this command is input during the IDLE state,the,Synchronous DRAM starts self-refresh operation.After the execution of this command,selfrefresh,continues while CKE is Low.Since self-refresh is performed internally and automatically,external refresh operations are unnecessary.,Self-Refresh ExitSELFX:When this command is executed during self-refresh mode,the Sync DRAM can exit from self-refresh mode.After exiting from self-refresh mode,the Sync DRAM enters the IDLE state.,no,Precharge,command is required after auto-refresh.,Mode Register,Special command to initialize the DRAM,Burst length,Interleaving,CAS Latency(read command to read data in clocks),For DDR,DLL reset is also here,MRS Block Diagram,Mode Register,Because the stored memory value is stored on a,Extended Mode Register,Special command to initialize DDR DRAM,DDR only,dont use for SDR,DLL Enable,Drive Strength,DRAM Interface,Command Signals,CAS#,RAS#,WE#,CS#,CS#+CAS#=Read,CS#+WE#+CAS#=Write,CS#+RAS#+CAS#=Refresh,CS#+RAS#=Activate,CS#+WE#=Burst Stop,CS#+WE#+RAS#=,Precharge,CS#+WE#+CAS#+RAS#=MRS or EMRS,All others:NOP,Other signals:,CLK,DATA,DQS,DRAM Interface,All signals go from the host to the memory except DQS and data which are bi-directional.,Read Cycle,Typical Read Cycle,Burst Length 4,CAS Latency=3,Write Cycle,Typical Write Cycle,Burst Length 4,Write latency is always zero,Data Clocking,CLK is always driven by the host,DQS is driven by whoever is driving the data,NV chip drives on write cycles,Memory chip drives on read cycles,This scheme is called“source-synchronous clocking”,Eliminates a lot of the timing headaches from SDR,Adds margin,Latencies,All kinds,Activate to,Precharge,Last write data to,precharge,Activate to Read,Activate to Write,Refresh cycle time,Refresh interval,Minimum row active time,Yadda,yadda,yadda,Controlled by PFB_TIMING0,PFB_TIMING1,PFB_TIMING2,Write Cycle,DLLs,A DLL is a Delay-Locked Loop,No transistor can switch in zero time,so there will be a delay between clock and DQS on reads,But,it would make it easier if DQS was always in phase with clock.,DLL-off clock-DQS delay not in the spec,Varies between memory vendors,Re-creates a delayed version of its input clock,Keeps DQS on reads aligned with clocks,Its an analog circuit and is sensitive to noise,Can lose lock on the input clock if the signal is not clean or the DLL power supply is noisy.,DLLs,DLL on,DLL off,tAA,tAC,tOH,tRCD,tRP,Set-up/Hold time,Vih,Vil,Voh,Vol,Ioh,Iol,Timing Parameters,SDRAM Timing Diagram,tAA,tAC,tOH,(SDRAM),Setup/hold time,Timing for latching data in Input buffer,CLK rising edge is strobe for data(SDRAM),DQS rising&falling edge is strobe for data(DDR SDRAM),During Setup&time,there is no abnormal signal allowed,VIH/VIL,VOH/VOL,IOH/IOL,DC Spec,Thanks!,