数字时钟54706.doc

设计一个含有时/分/秒的时钟
设计要求：1.具有'秒','分','时'时钟显示功能,在6个LED上显示
小时按24小时制计时.
2.具有校准功能
下面程序是没有控制系统在，而且有错误在，高手来帮我看看吧！！！
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity lb is
port (clk : in std_logic;
y0 : out std_logic_vector (7 downto 0);
ds : out std_logic_vector (4 downto 0));
end ;
architecture fly of lb is
signal d :integer range 0 to 5 ;
begin
process (clk)
variable a : integer range 0 to 4000;
begin
if clk'event and clk ='1' then
if a<4000 then
a:=a+1;
else a:=0;
if d0<9 then
d0<=d0+1;
else d0<=0;
if d1<5 then
d1<=d1+1;
else d1<=0;
if d2<9 then
d2<=d2+1;
else d2<=0;
if d3<5 then
d3<=d3+1;
else d3<=0;
if d4<3 then
d4<=d4+1;
else d4<=0;
if d5<2 then
d5<=d5+1;
else d5<=0;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end if;
end process;
process (d0)
begin
case d0 is
when 0 => y0<="0111111";
when 1 => y0<="0000110";
when 2 => y0<="1011011";
when 3 => y0<="1001111";
when 4 => y0<="1100110";
when 5 => y0<="1101101";
when 6 => y0<="1111101";
when 7 => y0<="0000111";
when 8 => y0<="1111111";
when 9 => y0<="1101111";
when others => y0<="0000000";
end case ;
end process ;
process (d1)
begin
case d1 is
when 0 => y1<="0111111";
when 1 => y1<="0000110";
when 2 => y1<="1011011";
when 3 => y1<="1001111";
when 4 => y1<="1100110";
when 5 => y1<="1101101";
when others => y1<="0000000";
end case ;
end process ;
process (d2)
begin
case d2 is
when 0 => y2<="0111111";
when 1 => y2<="0000110";
when 2 => y2<="1011011";
when 3 => y2<="1001111";
when 4 => y2<="1100110";
when 5 => y2<="1101101";
when 6 => y2<="1111101";
when 7 => y2<="0000111";
when 8 => y2<="1111111";
when 9 => y2<="1101111";
when others => y2<="0000000";
end case ;
end process ;
process (d3)
begin
case d3 is
when 0 => y3<="0111111";
when 1 => y3<="0000110";
when 2 => y3<="1011011";
when 3 => y3<="1001111";
when 4 => y3<="1100110";
when 5 => y3<="1101101";
when others => y3<="0000000";
end case ;
end process ;
process (d4)
begin
case d2 is
when 0 => y4<="0111111";
when 1 => y4<="0000110";
when 2 => y4<="1011011";
when 3 => y4<="1001111";
when others => y2<="1100110";
end case ;
end process ;
process (d5)
begin
case d3 is
when 0 => y5<="0111111";
when 1 => y5<="0000110";
when others => y5<="1011011";
end case ;
end process ;
问题补充：
process (clk)
variable q : std_logic ;
begin
if clk'event and clk ='1' then
q:=q+1;
case q is
when 1 => y<=y0; ds<="111110";
when 81 => y<=y1; ds<="111101";
when 161 => y<=y2; ds<="111011";
when 321 => y<=y3; ds<="110111";
when 401 => y<=y4; ds<="110111";
when 481 => y<=y5; ds<="101111";
q<='0';
end case ;
end if;
end process;
end;
提问者： yezh323 - 二级
最佳答案
2. 微秒模块
采用VHDL语言输入方式，以时钟clk，清零信号clr以及暂停信号STOP为进程敏感变量，程序如下：

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINSECONDb is
port(clk,clrm,stop:in std_logic;----时钟/清零信号
secm1,secm0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end MINSECONDb;

architecture SEC of MINSECONDb is
signal clk1,DOUT2:std_logic;

begin
process(clk,clrm)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
VARIABLE COUNT2 :INTEGER RANGE 0 TO 10 ;
begin

IF CLK'EVENT AND CLK='1'THEN
IF COUNT2>=0 AND COUNT2<10 THEN
COUNT2:=COUNT2+1;
ELSE COUNT2:=0;
DOUT2<= NOT DOUT2;
END IF;
END IF;

if clrm='1' then----当clr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if stop='1' then
cnt0:=cnt0;
cnt1:=cnt1;
end if;

if cnt1="1001" and cnt0="1000" then----当记数为98（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
--elsif cnt0="1001" then
--clk1<=not clk1;
else
cnt0:="0000";

if cnt1<"1001" then----高位小于9时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
secm1<=cnt1;
secm0<=cnt0;

end process;
end SEC;

3. 秒模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity SECOND is
port(clk,clr:in std_logic;----时钟/清零信号
sec1,sec0:out std_logic_vector(3 downto 0);----秒高位/低位
co:out std_logic);-------输出/进位信号
end SECOND;

architecture SEC of SECOND is
begin
process(clk,clr)
variable cnt1,cnt0:std_logic_vector(3 downto 0);---计数
begin
if clr='1' then----当ckr为1时，高低位均为0
cnt1:="0000";
cnt0:="0000";
elsif clk'event and clk='1' then
if cnt1="0101" and cnt0="1000" then----当记数为58（实际是经过59个记时脉冲）
co<='1';----进位
cnt0:="1001";----低位为9
elsif cnt0<"1001" then----小于9时
cnt0:=cnt0+1;----计数
else
cnt0:="0000";

if cnt1<"0101" then----高位小于5时
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
sec1<=cnt1;
sec0<=cnt0;

end process;
end SEC;

4. 分模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MINUTE is
port(clk,en:in std_logic;
min1,min0:out std_logic_vector(3 downto 0);
co:out std_logic);
end MINUTE;

architecture MIN of MINUTE is
begin

process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);
begin
if clk'event and clk='1' then
if en='1' then
if cnt1="0101" and cnt0="1000" then
co<='1';
cnt0:="1001";
elsif cnt0<"1001" then
cnt0:=cnt0+1;
else
cnt0:="0000";

if cnt1<"0101" then
cnt1:=cnt1+1;
else
cnt1:="0000";
co<='0';
end if;
end if;
end if;
end if;
min1<=cnt1;
min0<=cnt0;

end process;
end MIN;

5. 时模块程序清单

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity HOUR is
port(clk,en:in std_logic;----输入时钟/高电平有效的使能信号
h1,h0:out std_logic_vector(3 downto 0));----时高位/低位
end HOUR;

architecture hour_arc of HOUR is
begin
process(clk)
variable cnt1,cnt0:std_logic_vector(3 downto 0);----记数
begin
if clk'event and clk='1' then---上升沿触发
if en='1' then---同时“使能”为1
if cnt1="0010" and cnt0="0011" then
cnt1:="0000";----高位/低位同时为0时
cnt0:="0000";
elsif cnt0<"1001" then----低位小于9时，低位记数累加
cnt0:=cnt0+1;
else
cnt0:="0000";
cnt1:=cnt1+1;-----高位记数累加
end if;
end if;
end if;
h1<=cnt1;
h0<=cnt0;

end process;
end hour_arc;
6. 动态扫描模块
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity SELTIME is
port(
clk:in std_logic;------扫描时钟
secm1,secm0,sec1,sec0,min1,min0,h1,h0:in std_logic_vector(3 downto 0);-----分别为秒个位/时位；分个位/
daout:out std_logic_vector(3 downto 0);----------------输出
sel:out std_logic_vector(2 downto 0));-----位选信号
end SELTIME;
architecture fun of SELTIME is
signal count:std_logic_vector(2 downto 0);----计数信号
begin
sel<=count;
process(clk)
begin
if(clk'event and clk='1') then
if(count>="111") then
count<="000";
else
count<=count+1;
end if;
end if;
case count is
when"111"=>daout<= secm0;----秒个位
when"110"=>daout<= secm1;----秒十位
when"101"=>daout<= sec0;----分个位
when"100"=>daout<= sec1;----分十位
when"011"=>daout<=min0; ----时个位
when"010"=>daout<=min1;----时十位
when"001"=>daout<=h0;
when others =>daout<=h1;
end case;
end process;
end fun;
7. 报时模块

library ieee;
use ieee.std_logic_1164.all;
entity ALERT is
port(m1,m0,s1,s0:in std_logic_vector(3 downto 0);------输入秒、分高/低位信号
clk:in std_logic;------高频声控制
q500,qlk:out std_logic);----低频声控制
end ALERT;

architecture sss_arc of ALERT is
begin
process(clk)
begin

if clk'event and clk='1' then
if m1="0101" and m0="1001" and s1="0101" then----当秒高位为5，低位为9时且分高位为5
if s0="0001" or s0="0011" or s0="0101" or s0="0111" then---当分的低位为1或3或5或7时
q500<='1';----低频输出为1
else
q500<='0';----否则输出为0
end if;
end if;

if m1="0101" and m0="1001" and s1="0101" and s0="1001" then---当秒高位为5，低位为9时且分高位为5，----分低位为9时，也就是“59分59秒”的时候“报时”
qlk<='1';-----高频输出为1
else
qlk<='0';
end if;
end if;
end process;
end sss_arc;
8. 显示模块

library ieee;
use ieee.std_logic_1164.all;
entity DISPLAY is
port(d:in std_logic_vector(3 downto 0);----连接seltime扫描部分d信号
q:out std_logic_vector(6 downto 0));----输出段选信号（电平）
end DISPLAY;
architecture disp_are of DISPLAY is
begin
process(d)
begin

case d is
when"0000" =>q<="0111111";--显示0
when"0001" =>q<="0000110";--显示1
when"0010" =>q<="1011011";--显示2
when"0011" =>q<="1001111";--显示3
when"0100" =>q<="1100110";--显示4
when"0101" =>q<="1101101";--显示5
when"0110" =>q<="1111101";--显示6
when"0111" =>q<="0100111";--显示7
when"1000" =>q<="1111111";--显示8
when others =>q<="1101111";--显示9
end case;
end process;
end disp_are;