IC封装设计与仿真.pdf

IC封装设计与仿真：装设计电磁仿真装热仿真结构仿真1一IC封装设计IC封装内部结构:Lead金线LC元件SIPIC封装设计IC封装发展趋势:3D int erconnect Technol ogy Roadmap芯片封装发展四阶段：第一阶段，20世纪80年代前,第二阶段，20世纪80年代后,第三阶段，20世纪90年代后,以插装型为主；以表面安装类型的四边引线封装为主;以面阵列封装形式为主；第四阶段，21世纪，3D封装为主。First revolutionThrough hole to surf ace mount(DIP to QFP.SOP)T8OP右 SU8p J8U6I(QFP to BGA)Peripheral lead type to ball array surf ace mount typefcbgaWSecond revolution9Whats Next!MCPMas：20 即 te663D TSV StackMHoles:50 pm pD-WLP55Holes:2oopm Era刘痴-第p上二PassiIIL虚滥冒0 Embeded memoiyPOP3DSFWLPMEMS3D CIS3D LogioSiP”UH 竽,析怪.8？.芯 e空p 15“3D Fusion3DRF-SIPPassiveWL-CSP CIS TSVCISMEMS2008 2009 2010 2011Mas:5-20 pm Holes:100KOJcumnDJ t ioo pm四(UltimaT3D IC|W-Ui LogicAnalog:晶;晶同Vias 1C0K t 20 pmRF rDRAM3-MPUas=1C-30 pm I Holes 100 ti one of cm*(Murca nVR/GNO Maiws wlwch willtntcvnty A5C f leerleal lab could f tntf out tte resonant mode，”PWR/GNO iet In a PKGtry to Mid via*or tl-torf e to rannia the rMotMrt Antof t Slwava f t Sirity Povr SI ar*two powerf ul f requency.o:封装电磁仿真Package IBIS Model:odta、_ 0 a*osv iff，9 0 c300。白。8BOOQ一 夫一卜 3%.*m WorkspaceE Workspace一：,Q qf n.pkg(，IBIS Ver )File Name J Ne Rev HDate)!Source NotesO CopyrightB Def ine Package Model QFN I Manuf acturer，Oem(I Desalption(I Number Of Pins(I Pin Numbers Modd DataI I Inductance Matrix()Capacitance Matrix()Resistance Matrix()End Model Data I End Package ModdL o End0QQ1 QQQ2 0003 004 0005 0QQ6 0Q07 00Q8 OOQQ 0010 QQ11 0012 0013 014 0015 0016 0017 0018 010 0020 0021 022 0023 0024 0Q25 0026 027 0028 nnooIBIS Ver-470File Name qfn.pkgFile Rev 1.0Date Sun May 13 23:19:39 2012Source Ansoft Q3D Extractor 7.0froa project QFNNotesCopyright Ansoft Corporation 1998-2003.All rights reserved.Define Package Model QFN ManufacturerJ UnknownOEM UnknownDescription NoneKujnber Of Pins 33Pm Numbers229218132030321333 19260722=ADJRSSI9=AS21=BBAGC8=CP1=dujunyl3=du*my_320=duiMiy_2030=dxuwny_3032=dunmy_3213=DVDD33=GND19=HOLDAGC26=OUTIMOT-AUTTDESD STRUCTUREPULL UPPULL DOWNSWITCHING CHARACTERISTICS:i封装热仿真封装热仿真的必要性电壬封装的失效率与热成正比，而且与封装的 最嵩温度成指数增长失效率可以表示为：F=Ae-EmF二失效率,A二常数E=电子激活能量(eV)K=波尔兹曼常数(8.63e-5eV/K)T=节点(junct ion)温度(以K为单位)封装潟度对失效的影响(每百万个元件工作lOOOhr失效的数口)ComponentTemperature=25CTemperature=75CThick film resistor515Chip capacitor1025Power transistor50300Diode19Logic ICs-SSI1251125Logic ICs-MSI2502250Logic ICs-LSI5004500Source:C.A.Harper,Handbook of Thick Film Hybrid Microelectronics100 110 120 130 140 150 160Junct ion Temperat ure(C)Temperature Vibration Humidity DustSource:U.S.Airforce Avionics Integrity Program(Reynell.M.,1990)封装热仿真基本理论:热传递三种方式A传导JTjTaT.dQ=kATj-Tadk为材料导热系数（W/m-C）A为热传导面积为高温面的温度 为低温面的温度 为材料厚度嬲f对流-传导T对流h为对流换热系数A为换热面面积Ts为固体表面的温度Ta为流体温度Q=hA(Ts-Ta)Q=eoAK(r：-T；)辐射芯片散热解塑封金 银锡7厂*好中2f ft T.4吃Gja=QJcGcaPCB为辐射率（黑度）C T为斯蒂芬-波尔兹曼常数，约为5.6 7X10-8W/m2.K 4Ai为辐射面i的面积Fij为由辐射面i到辐射面j的形状系数Ti为辐射面i的绝对温度Tj为辐射面j的绝对温度封装热仿真封装热仿真步骤:软件：C adence;Autocad;ProE,UG 文件格式：Idf,igs,sat,step,dxf建模求解后处理在热分析软件中直接建实体模型,或通过其他软件导入封装结构；定义材料热性能参数定义求解域，求解类型；施加热载荷，定义边界条件;划分网格，定义收敛标准；求解图形显示温度场；节点温度hot point；计算热阻；列表各面的热流率，换热系数封装热仿真封装热阻的定义：T.-ic封装而言，最重要的参数是由芯片接面到固定位置的热阻，其定义如右：ejX=-热阻值。或是R表示，Tj=Die发热部位的温度值die(junction)，Tx=某参考 Q点的温度值，P=芯片的功耗。常用的定义：6 ja,0 jb,Bjc,Wjb,W jtDef inition of RJMDeHnttion ofDef inition of f t1mWr=Q封装热仿真封装热阻模型:0 jx使用的局限性Convection/RadiationConvection/RadiationConductionConvection Conduction RadiationConductionJunction qJX试图采用简单的热阻表示复杂的芯片传热现象 芯片内部的热传现象非常复杂，无法使用热阻来完美表示；热阻Qjx无法用于准确预测芯片的温度，只能提供定性的热性能对比;如需准确预测特定工况下芯片的温度，我们需要其它的方法封装热仿真封装热阻模型：芯片的详细模型Epoxy-basedEncapsulaiftvBT DielectricSilicon Die Die 詈丁吁&GoldSolder Balls(37Pb/63Sn)BottomSpreaderSignal ViasThermalViasPower&GroundPlanes模型包含几乎所有的详细特征,如金丝，锡球,芯片(die),底层等.用于封装层次的建模,描述以及测量确认等.-精度高-边界条件无关,与网络模型不同-计算时间比简化的模型多-仅仅用于非常重要的封装封装热仿真封装热阻模型：DELPHI模型 Tlie compact model is generated from analysis,and not testing.Experiments are relevant for validation piuposes only.Tlie starting point fbr the process is the availability of an experimentally validated detailed thennal model(see 4.2).The analytical procedure used to derive the compact model involves a statistical process of optimization.The model does not contain any artifacts from the enviionment.Error estimate is an intrinsic pail of the model generation process.Like the other compact model approaches,the DELPHI approach masks data about the package that the CTM supplier may regard as proprietaiy.封装热仿真热阻模型的提取：DELPHI模型封装热仿真4-40.Ef f ect of Board Temperature Rise on Thermal Resistance of 132-Lead PQFP with Copper and Alloy 42-Lead Frames(M/90)2qs-CBE-9Ml cQqulv-F co-5 3封装热仿真封装热管理优化：材料选择D槛水导热率(W/mlMold树脂导热率(W/mK：Subst rate板材导热率(W/irK)材料导热率(W/mK)DAD902.90EME-G700L type Y0.96DS7409HG B0.6 0铜380DAD8714.58EME-G6 00F Type B0.94DS7409HG B(S：0.80金32484-12.50EME-G6 000.92DS7409HG B(L；0.70Si153/258352L5.60EME-G6 30 Type AY0.92MC L-E-6 79GT0.82119/778200T2.50EME-6 6 00H type R0.88HL832-A0.4498/127529HT6.00EME-G7000.88ELC-4785-GS0.6 8GaAs4683602.90K L-1000-4T0.85HL8320.30Sn6 3Pb3750.982901.6 0K L-1000-200.85HL832-EX0.5583401.00EME 6 6 00C S0.82HL832-HS0.50LTC C GL771284-30.80K L-4500-F0.80HL832-TF0.50LTC C GL3304.384-3J0.50K L-G450H0.80HL832-TS0.30HTC C A44014QMI538NB0.40EME-E500 type HM0.78HL832-NS0.558900NC0.30K L-4000-10.75HL832-NS-LC0.6 02815A20.00K L-4500-10.75HL832-ES0.7590055.00K L-4500-1NT0.7591441.20EME-6 300HS0.6 7PbAg25Sn253.00EME-6 300 Type H-L0.6 7PbSnlO46.00EME-6 300 Type HR0.6 7封装热仿真封装热管理优化：材料选择，结构优化原设计优化1优化2DA胶水84-1DAD87DAD87散热pad无无有U1结温()50.0449.8446.760 ja(/W)150.4148.4117.6优化1.3%20.8%U2结温()49.6349.4846.430 ja(/W)101.597100.5679.38优化1.0%21.1%封装结构仿真封装结构仿真封装失效模式:封装结构仿真封装失效的来由:封装体是由不同的材料堆叠而成，当在生产或使用过程中 有热产生时，由于材料的C TE不匹配，会在封装结构中产生热应 力，导致一系列的可靠性问题，如warpage,delamination,crack等等。(a)Package modelWarpage contourbam!proptnw of consanxnK of&pxkjf eCccEpcctan琳(Mb)CTt Tt(HX)(*o 1Chip墨co131000286号EpoxyQMI5%90093 17431030CocopcwdGE-50621000 a 25*C 9Wa 2M,C11,39170030Dbelectnc GX 560 16015302Diekox GX13Finn iXY3,】1 Z 60 2516002Sub$3Xt11700017*0344BT-core CCLHL852NX-AFifurelW 14 4Z32 150 xo02$44日皿山 AUS410320051 15310503封装结构仿真Ansys操作步骤:封装结构仿真封装结构仿真实例:封装仿真的目的：1.优化封装结构，降低失效风险2.查找失效根源，解决失效问题MaterialYoungs Modulus E(Mpa)Poissons R atioC TE(ppm/C)dimension(iron)Solder Bump332360.3521D=0.2,h=0.15Substrate240440.281410 x10 x0.25Si Die13936 00.32.84.8x4.8x0.25UnderFill6 0000.35300.345封装结构仿真封装曲翘云图:曲翘最大在substrate边角上:无Underfill：18.3um有Underfill：25.8umANSYS封装结构仿真等效应力云图:最大von mises在FC与Sorder Bump边界上：无Underfill：Max(198Mpa),Min(15421Pa)有Underfill：Max(74Mpa)，Min(7404Pa)封装结构仿真切应力云图:最大剪切应力在边角的Bump与die的结合面上:无Underfill：39.2Mpa有Underfill：3.26 Mpa八NAYS无 underfil l有underfil lWhat can I do f or youTools:AutoC AD,ProE C adence APD,Sip EPD,C am350Package design,Substrate design,C OB PC B designTools:Ansoft Q3D,HFSS,SIwave,Designer Angilent ADS,C adence SI0 Preliminary and Post Layout Electrical Design Parameters R LC Extraction,S-parameters,PDN C urrent Distribution,IR drop,R esonance,EMI/EMC,Design Output:Bond DiagramPackage Outline DrawingManufacture DrawingsDwg/Dxf/igs/GerbersTools:Ansys Mechanical/StructureTools:Icepak,ANSYS,FlothermWarpage and stress analysis Design Optimization,Material SelectionThermal Performace Sensitivity Study,Package Thermal Model Extraction,Jedec/System Environment Simulation