简单计算机系统专业课程设计计算机组成实验C.doc

计算机组成试验 C课程设计适用专业： 电子信息类专业专 业: * 班 级: * 学 号: * 姓 名: * 指导老师: * 试验学期: -第1学期西南交通大学信息科学和技术学院简化计算机系统设计一. 试验目标：经过学习简单指令系统及其各指令操作步骤，用 VHDL 语言实现简单处理器模块，并经过调用存放器模块，将处理器模块和存放器模块连接形成简化计算机系统。二. 试验内容1. 用 VHDL 语言实现简单处理器模块。2. 调用存放器模块设计 25616 存放器模块。3. 将简单处理器模块和存放器模块连接形成简单计算机系统。4. 将指令序列存入存放器，然后分析指令实施步骤。三. 预习要求：1、学习简单指令集。2、学习各指令操作步骤。四. 试验汇报1. BLOCK 图图1 原理图内存文件：图2 内存文件.Mif2.程序设计LIBRARY ieee;USE ieee.std_logic_1164.ALL;PACKAGE mypack ISCONSTANT idle : std_logic_vector(3 DOWNTO 0) :=0000;CONSTANT load : std_logic_vector(3 DOWNTO 0) :=0001;CONSTANT move : std_logic_vector(3 DOWNTO 0) :=0010;CONSTANT addx : std_logic_vector(3 DOWNTO 0) :=0011;CONSTANT subp : std_logic_vector(3 DOWNTO 0) :=0100;CONSTANT andp : std_logic_vector(3 DOWNTO 0) :=0101;CONSTANT orp : std_logic_vector(3 DOWNTO 0) :=0110;CONSTANT xorp : std_logic_vector(3 DOWNTO 0) :=0111;CONSTANT shrp : std_logic_vector(3 DOWNTO 0) :=1000;CONSTANT shlp : std_logic_vector(3 DOWNTO 0) :=1001;CONSTANT swap : std_logic_vector(3 DOWNTO 0) :=1010;CONSTANT jmp : std_logic_vector(3 DOWNTO 0) :=1011;CONSTANT jz : std_logic_vector(3 DOWNTO 0) :=1100;CONSTANT read : std_logic_vector(3 DOWNTO 0) :=1101;CONSTANT write : std_logic_vector(3 DOWNTO 0) :=1110;CONSTANT stop : std_logic_vector(3 DOWNTO 0) :=1111;END mypack;LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_unsigned.ALL;USE WORK.mypack.ALL;-cpu实体申明-ENTITY cpu2 ISPORT( reset : IN std_logic; -清零信号低有效 clock : IN std_logic; -时钟信号 Write_Read: OUT std_logic; -读写信号,1为写 M_address: OUT std_logic_vector(11 DOWNTO 0); -地址线 M_data_in: IN std_logic_vector(7 DOWNTO 0); -数据输入线 M_data_out: OUT std_logic_vector(7 DOWNTO 0); -数据输出线 overflow: OUT std_logic);-溢出标志END cpu2;-cpuRTL级行为描述-ARCHITECTURE RTL of cpu2 IS SIGNAL IR: std_logic_vector(15 DOWNTO 0); -指令寄存器 SIGNAL MDR: std_logic_vector(7 DOWNTO 0); -数据寄存器 SIGNAL MAR: std_logic_vector(11 DOWNTO 0); -地址寄存器 SIGNAL status: integer RANGE 0 TO 6; -状态寄存器 BEGIN status_change: PROCESS(reset, clock, status ) BEGINIF reset = 0 THEN status status IF IR(15 DOWNTO 12) = Stop THEN status = 1; ELSE status CASE IR(15 DOWNTO 12) ISWHEN Read|Write|Jmp|Jz|Swap =status status IF IR(15 DOWNTO 12)= Swap THEN status = 0; ELSE status status CASE IR(15 DOWNTO 12) ISWHEN Read|Write =status status status = 0; END CASE; ELSENULL;END IF; END PROCESS status_change; seq: PROCESS(reset,clock) VARIABLE PC:std_logic_vector(11 DOWNTO 0); -程序计数器 VARIABLE R0,R1,R2,R3: std_logic_vector(7 DOWNTO 0); -通用寄存器 VARIABLE A: std_logic_vector(7 DOWNTO 0); -临时寄存器 VARIABLE temp: std_logic_vector(8 DOWNTO 0); -临时变量 BEGIN IF(reset=0) THEN- 清零 IR 0); PC := (OTHERS=0); R0 := (OTHERS=0); R1 := (OTHERS=0); R2 := (OTHERS=0); R3 := (OTHERS=0); A := (OTHERS=0); MAR 0); MDR 0); ELSIF(clockevent AND clock=1) THEN overflow -状态0 IR -状态1 IF (IR(15 DOWNTO 12) /= stop) THEN MAR R0:= 0000 & IR(11 DOWNTO 8); WHEN shlp|shrp = CASE IR(11 DOWNTO 10) IS- Rx to A WHEN 00= A:= R0; WHEN 01= A:= R1; WHEN 10= A:= R2; WHEN OTHERS = A:= R3; END CASE; WHEN Move|addx|subp|andp|orp|xorp|Swap= CASE IR(9 DOWNTO 8) IS- Ry to A WHEN 00= A:=R0; WHEN 01= A:=R1; WHEN 10= A:=R2; WHEN OTHERS= A:=R3; END CASE; WHEN OTHERS = NULL; END CASE; WHEN 2= -状态2 CASE IR(15 DOWNTO 12) IS WHEN addx = - Rx:= Rx + A; CASE IR(11 DOWNTO 10) IS WHEN 00= temp := (R0(7) & R0(7 DOWNTO 0) + (A(7) & A(7 DOWNTO 0); R0:=temp(7 DOWNTO 0); overflow temp :=(R1(7) & R1(7 DOWNTO 0) + (A(7) & A(7 DOWNTO 0); R1:=temp(7 DOWNTO 0); overflow temp :=(R2(7) & R2(7 DOWNTO 0) + (A(7) & A(7 DOWNTO 0); R2:=temp(7 DOWNTO 0); overflow temp :=(R3(7) & R3(7 DOWNTO 0) + (A(7) & A(7 DOWNTO 0); R3:=temp(7 DOWNTO 0); overflow - Rx:= Rx - A; CASE IR(11 DOWNTO 10) IS WHEN 00= temp :=(R0(7) & R0(7 DOWNTO 0) + NOT(A(7) & A(7 DOWNTO 0) + 1; R0:=temp(7 DOWNTO 0); overflow temp :=(R1(7) & R1(7 DOWNTO 0) + NOT(A(7) & A(7 DOWNTO 0) + 1; R1:=temp(7 DOWNTO 0); overflow temp :=(R2(7) & R2(7 DOWNTO 0) + NOT(A(7) & A(7 DOWNTO 0) + 1; R2:=temp(7 DOWNTO 0); overflow temp :=(R3(7) & R3(7 DOWNTO 0) + NOT(A(7) & A(7 DOWNTO 0) + 1; R3:=temp(7 DOWNTO 0); overflow CASE IR(11 DOWNTO 10) IS WHEN 00= R0:= A; WHEN 01= R1:= A; WHEN 10= R2:= A; WHEN OTHERS= R3:= A; END CASE; WHEN shrp = CASE IR(11 DOWNTO 10) IS WHEN 00= R0:= 0 & A( 7 DOWNTO 1 ); WHEN 01= R1:= 0 & A( 7 DOWNTO 1 ); WHEN 10= R2:= 0 & A( 7 DOWNTO 1 ); WHEN OTHERS= R3:= 0 & A( 7 DOWNTO 1 ); END CASE; WHEN shlp = CASE IR(11 DOWNTO 10) IS WHEN 00= R0:= A( 6 DOWNTO 0 ) & 0; WHEN 01= R1:= A( 6 DOWNTO 0 ) & 0; WHEN 10= R2:= A( 6 DOWNTO 0 ) & 0; WHEN OTHERS= R3:= A( 6 DOWNTO 0 ) & 0; END CASE; WHEN andp = -Rx:= Rx AND A; CASE IR(11 DOWNTO 10) IS WHEN 00= R0:=R0 AND A; WHEN 01= R1:=R1 AND A; WHEN 10= R2:=R2 AND A; WHEN OTHERS= R3:=R3 AND A; END CASE; WHEN orp = -Rx:= Rx OR A; CASE IR(11 DOWNTO 10) IS WHEN 00= R0:=R0 OR A; WHEN 01= R1:=R1 OR A; WHEN 10= R2:=R2 OR A; WHEN OTHERS= R3:=R3 OR A; END CASE; WHEN xorp = -Rx:= Rx XOR A; CASE IR(11 DOWNTO 10) IS WHEN 00= R0:=R0 XOR A; WHEN 01= R1:=R1 XOR A; WHEN 10= R2:=R2 XOR A; WHEN OTHERS= R3:=R3 XOR A; END CASE; WHEN Swap = -Swap: Rx to Ry; CASE IR(11 DOWNTO 8) IS WHEN 0100= R0:=R1; WHEN 1000= R0:=R2; WHEN 1100= R0:=R3; WHEN 0001= R1:=R0; WHEN 1001= R1:=R2; WHEN 1101= R1:=R3; WHEN 0010= R2:=R0; WHEN 0110= R2:=R1; WHEN 1110= R2:=R3; WHEN 0111= R3:=R1; WHEN 1011= R3:=R2; WHEN 0011= R3:=R0; WHEN OTHERS= NULL; END CASE; WHEN OTHERS = NULL; END CASE; WHEN 3= -状态3 CASE IR(15 DOWNTO 12) IS WHEN Swap= - Swap: A to Rx CASE IR(11 DOWNTO 10) IS WHEN 00= R0:=A; WHEN 01= R1:=A; WHEN 10= R2:=A; WHEN OTHERS= R3:=A; END CASE; WHEN jmp|Jz|Read|Write = IR(7 DOWNTO 0) NULL; END CASE; WHEN 4= -状态4 CASE IR(15 DOWNTO 12) IS WHEN jmp = - 无条件转移指令 PC := IR(11 DOWNTO 0); MAR - 条件转移指令 IF(R0=00000000) then PC := IR(11 DOWNTO 0); MAR = IR(11 DOWNTO 0); else MAR MAR MAR = IR(11 DOWNTO 0); MDR NULL; END CASE; WHEN 5 = -状态5 MAR -状态6 CASE IR(15 DOWNTO 12) IS WHEN Read = R0 := M_data_in;WHEN OTHERS= NULL; END CASE; END CASE; END IF; END process seq;comb: PROCESS (reset, status)BEGIN IF (reset = 1 AND status = 5 AND IR(15 DOWNTO 12)= Write ) THEN Write_Read = 1; ELSE Write_Read = 0; END IF;END PROCESS comb;M_address = MAR;M_data_out = MDR;END RTL;3.仿真波形图图3 波形图1图4 波形图2解释以下：图5 指令含义4.试验感想经过本试验我学到很多有用知识，不仅提升了我系统设计和软件编程能力，还让我对计算机组成原理试验课程有了更一步掌握和认识。在本课程设计中，除了对CPU内部运算器，控制器和存放器之间联络和分工合作了解之外，在建立波形图时，因为受平日建图影响，忘记添加CPU内部寄存器组，另外在添加寄存器信号后，还要将相同划成一个GROUP，在这之前练习中，我是没有接触过。这次练习掌握部分新知识，相信在未来对我会有巨大帮助。