电子技术-芯片资料-74LS114.pdf

TL/F/1017654LS114 Dual JK Negative Edge-Triggered Flip-Flopwith Common Clocks and ClearsJune 198954LS114Dual JK Negative Edge-TriggeredFlip-Flop with Common Clocks and ClearsGeneral DescriptionThe LS114 features individual J,K and set inputs and com-mon clock and common clear inputs.When the clock goesHIGH the inputs are enabled and data will be accepted.Thelogic level of the J and K inputs may be allowed to changewhen the Clock Pulse is HIGH and the bistable will performaccording to the truth table as long as the minimum setuptimes are observed.Input data is transferred to the outputson the negative-going edge of the clock pulse.Connection DiagramDual-In-Line PackageTL/F/101761Order Number 54LS114DMQB,54LS114FMQB or 54LS114LMQBSee NS Package Number E20A,J14A or W14BLogic SymbolTL/F/101762VCCePin 14GNDePin 7Pin NamesDescriptionJ1,J2,K1,K2Data InputsCPClock Pulse Input(Active Falling Edge)CDDirect Clear Input(Active LOW)SD1,SD2Direct Set Inputs(Active LOW)Q1,Q2,Q1,Q2OutputsC1995 National Semiconductor CorporationRRD-B30M105/Printed in U.S.A.Absolute Maximum Ratings(Note)If Military/Aerospace specified devices are required,pleasecontacttheNationalSemiconductorSalesOffice/Distributors for availability and specifications.Supply Voltage7VInput Voltage7VOperating Free Air Temperature Range54LSb55C toa125CStorage Temperature Rangeb65C toa150CNote:The Absolute Maximum Ratings are those valuesbeyond which the safety of the device cannot be guaran-teed.The device should not be operated at these limits.Theparametric values defined in the Electrical Characteristicstable are not guaranteed at the absolute maximum ratings.The Recommended Operating Conditions table will definethe conditions for actual device operation.Recommended Operating ConditionsSymbolParameter54LS114UnitsMinNomMaxVCCSupply Voltage4.555.5VVIHHigh Level Input Voltage2VVILLow Level Input Voltage0.7VIOHHigh Level Output Currentb0.4mAIOLLow Level Output Current4mATAFree Air Operating Temperatureb55125Cts(H)Setup Time20nsts(L)Jn or Kn to CP20th(H)Hold Time0nsth(L)Jn or Kn to CP0tw(H)CP Pulse Width20nstw(L)15twCD or SDn Pulse Width15nsElectrical CharacteristicsOver recommended operating free air temperature range(unless otherwise noted)SymbolParameterConditionsMinTypMaxUnits(Note 1)VIInput Clamp VoltageVCCeMin,IIe b18 mAb1.5VVOHHigh Level Output VoltageVCCeMin,IOHeMax,2.5VVILeMaxVOLLow Level Output VoltageVCCeMin,IOLeMax,0.4VVIHeMin0.5IIInput CurrentMaxVCCeMax,VIe10V;Jn,Kn Inputs0.1mAInput VoltageSD1,SD2 Inputs0.3mACD Input0.6mACP Input0.8mAIIHHigh Level Input CurrentVCCeMax,VIe2.7V;Jn,Kn Inputs20mASD1,SD2 Inputs60mACD Input120mACP Input160mANote 1:All typicals are at VCCe5V,TAe25C.2Electrical Characteristics(Continued)Over recommended operating free air temperature range(unless otherwise noted)SymbolParameterConditionsMinTypMaxUnits(Note 1)IILLow Level Input CurrentVCCeMax,VIe0.4V Jn,Kn Inputsb0.4mASD1,SD2 Inputsb0.8mACD Inputb1.6mACP Inputb1.44mAIOSShort CircuitVCCeMaxb20b100mAOutput Current(Note 2)ICCSupply CurrentVCCeMax,VCPe0V8.0mANote 1:All typicals are at VCCe5V,TAe25C.Note 2:Not more than one output should be shorted at a time,and the duration should not exceed one second.Switching CharacteristicsVCCe a5.0V,TAe a25C(See Section 1 for Test Waveforms and Output Load)SymbolParameterRLe2k,CLe15 pFUnitsMinMaxfmaxMaximum Count Frequency30MHztPLHPropagation Delay16nstPHLCP to Q or Q24tPLHPropagation Delay16nstPHLCD or SDn to Q or Q24Truth TableInputsOutputtntna1JKQLLQnLHLHLHHHQnAsynchronous Inputs:LOW input to SD sets Q to HIGH levelLOW input to CD sets Q to LOW levelClear and Set are independent of clockSimultaneous LOW on CD and SDmakes both Q and Q HIGHHeHIGH Voltage LevelLeLOW Voltage LeveltneBit time before clock pulse.tna1eBit time after clock pulse.3Logic Diagram(one half shown)TL/F/101763Physical Dimensionsinches(millimeters)Ceramic Leadless Chip Carrier(E)Order Number 54LS114LMQBNS Package Number E20A4Physical Dimensionsinches(millimeters)(Continued)14-Lead Ceramic Dual-In-Line Package(J)Order Number 54LS114DMQBNS Package Number J14A554LS114 Dual JK Negative Edge-Triggered Flip-Flopwith Common Clocks and ClearsPhysical Dimensionsinches(millimeters)(Continued)14-Lead Ceramic Flat Package(W)Order Number 54LS114FMQBNS Package Number W14BLIFE SUPPORT POLICYNATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORTDEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONALSEMICONDUCTOR CORPORATION.As used herein:1.Lifesupportdevicesorsystemsaredevicesor2.A critical component is any component of a lifesystems which,(a)are intended for surgical implantsupport device or system whose failure to perform caninto the body,or(b)support or sustain life,and whosebe reasonably expected to cause the failure of the lifefailure to perform,when properly used in accordancesupport device or system,or to affect its safety orwith instructions for use provided in the labeling,caneffectiveness.be reasonably expected to result in a significant injuryto the user.National SemiconductorNational SemiconductorNational SemiconductorNational SemiconductorCorporationEuropeHong Kong Ltd.Japan Ltd.1111 West Bardin RoadFax:(a49)0-180-530 85 8613th Floor,Straight Block,Tel:[phone]Arlington,TX 76017Email:Ocean Centre,5 Canton Rd.Fax:[phone]Tel:[phone]Deutsch Tel:(a49)0-180-530 85 85Tsimshatsui,KowloonFax:1(800)737-7018EnglishTel:(a49)0-180-532 78 32Hong KongFran3ais Tel:(a49)0-180-532 93 58Tel:[phone]ItalianoTel:(a49)0-180-534 16 80Fax:[phone]National does not assume any responsibility for use of any circuitry described,no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.