LDOArchitectureReviewForRecordingFinal30.pptx

LDO Architecture ReviewHow different LDO architectures influence performance1OverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup2Standard LDO Architecture3Pass Device controls current flow from VIN to VOUTFeedback Resistors determine output voltageError Amplifier forces FB node voltage to match voltage reference.Voltage Reference provides accurate DC voltage.OverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup4Simplified AC Model5This system block diagram represents a simplified small-signal AC model of a typical LDO.Ideally,VIN has no impact on the loop.AEA and Gm form a high-gain path necessary for accurate regulation.Output impedance(ZOUT)will have significant impact on the performance of the loop.AFB is the gain formed by the feedback resistors.Simplified AC Model With Input Coupling6In the real world,VIN will couple into the loop and degrade loop performance.Simplified AC Model7OverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup8MOSFET Pass Devices9P-Type MOS(PMOS):Very common.Low VDO,low Iq,no charge pump or bias rail requirements.N-Type MOS(NMOS):Lowest VDO possible,however,error amplifier needs higher voltage than VIN to drive it.PNP:Can achieve higher voltage depending on process capability.PMOS Pass Device10PMOS Advantages:SimpleLowest cost structurePMOS Disadvantages:RDSON is higher vs.NMOSCommon-drain structure gives higher output impedanceNMOS Pass Device11NMOS Advantages:Better RDS(on)per unit areasmaller die sizeCommon Drain Structure gives low output impedanceWide range of stability vs COUTLow output impedanceDisadvantages:Needs a charge pump or external bias rail to achieve low VIN VOUTPNP Pass Device12PNP Advantages:Can achieve higher VIN voltages Error amplifier design in bipolar process can achieve low noiseDisadvantages:Difficult to design for low IqDropout can be higher for light loadsOverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup13Dropout14Dropout,or VDO,is the minimum voltage necessary from VIN to VOUT to maintain regulation.PSRR,noise,load regulation and transient response are all significantly worse when device is in dropout.Dropout -VDO=VIN VOUT when VOUT drops from nominal regulation voltageFor a MOSFET pass element,pass device enters linear region when the LDO goes into dropout.In dropout,VDO is proportional to load currentDropout Dependancies For MOS15Dropout vs.Temperature increases because mobility of pass device is reduced.TLV73333 VDO vs.IOUTTLV73318 VDO vs.IOUTDropout For PNP16For a PNP pass device,when VCE is low,the device is in“saturation”.In this state,the voltage is not directly proportional to the output current.Many devices,such as the TPS7A49,use an anti-saturation circuit to improve recovery time out of saturation.TPS7A49 VDO vs.IOUTOverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup17Intrinsic Noise VS Input Signal Coupling LDO output voltage disturbances that are not load-related are composed of Input Signal Coupling that is coupled through the pass device,as well as Intrinsic Noise that comes from primarily the reference and error amplifier.Power Supply Rejection Ratio(PSRR)determines how much noise from the input couples into the output.Intrinsic Noise(or simply“Noise”)is generated primarily from the internal reference and error amplifier.LDO Noise,Dominant Noise Sources19Noise is combined into total output noise for the noise specification.Typically noise is specified in total RMS noise from 10 Hz to 100 kHzDominant noise sources are the voltage reference and error amplifier.Noise Reduction(NR)with Bandgap RC Filter 20The Reference Voltage noise can be filtered with an RC filter.This can be external or internal.On external devices,add a capacitor to the NR pin.Increasing CNR pushes noise lower.However,noise in this region is limited by thermal noise from the error amplifier.CNRLow Noise CNR and Error Amplifier Example TPS7A9121CNR reduces reference voltage noiseNoise Reduction(NR)with Internal Bandgap RC Filter -LP590722NR filter is integrated with very large(1 G)filter resistorNo CNR necessarySimplified SchematicVoltage Reference provides accurate DC voltage.Feedback ResistorsEffect on NoiseLDO Intrinsic noise is dominated by noise from the reference and the error amplifier.In a standard LDO,decreasing AFB(feedback resistor attenuation)will result in higher noise at the output.Higher output voltages(lower AFB)will have higher noise gain.Assume:input noise=0 DC voltages=0Adding a CFF reduces Closed-Loop Gain24CFF brings resistor attenuation(AFB)to 1 at high frequencyCFF can also improve transient responseLow Noise Example:TPS7A4700 36V 1A 4 Vrms25To reduce closed-loop gain,and therefore noise,some devices gain up the reference,and then use the RC filter.The bandgap voltage reference is gained up with internal resistors.The effective reference voltage is then filtered after the reference amplifier.Error AmpReference AmpOverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup26PSRR27PSRR(Power Supply Ripple Rejection)represents the ability of the LDO to filter input voltage changes.This is critical for low-noise applications.Typical PSRR Curve28Region 1 is determined by:PSRR or Thermal Coupling into ReferenceRegion 2 is determined by:Open-Loop Gain of Error AmplifierRegion 3 is determined by:Parasitic capacitance and output capacitorHigh PSRR with Additional Pass Device29Some devices use an additional pass element,connected as a“cascode”device.Using a cascode pass device can improve the pass device output impedance,and therefore,the PSRR.Examples of this are the LP38798(shown),TPS7A81 and TLV707.OverviewGeneral Block Diagram ReviewSmall Signal ModelLDO Pass Devices PMOSNMOSBJTLDO Performance DropoutNoise PSRRStartup30How Startup Works(ideally)31VIN is driven highIdeal LDO startup behavior occurs when VFB tracks the reference from 0 V to the final value.VREF begins rampingVFB track VREFVOUT ratiometrically follows VFBInrush Current During Startup 32For an ideal startup,the current through the load capacitor is constant.ICOUTILOADIINWhen the output ramps,current is supplied to both the output capacitorAnd the load.Leading to a high current ramp.Non-ideal Startup33Many LDOs have a high dV/dT,or“jump”at startup.This is commonly due to limited common mode range of the error amplifier.For an NMOS input pair,VFB cannot track VREF until VREF VTH+VOV Non-ideal Startup34The high dV/dt change on the output will result in a peak of current into the output capacitor.Output capacitor current will flow from the input,causing a peak of current at the input.The input current will lead to a drop in the input voltage,which can create problems on the input rail.Ideal Startup example:TPS74X35The TPS74X family has constant-current soft-start capacitor charging,leading to well-controlled startup behavior.Copyright 2017 Texas Instruments Incorporated.All rights reserved.This material is provided strictly“as-is,”for informational purposes only,and without any warranty.Use of this material is subject to TIs Terms of UseTerms of Use,viewable at TI.com