21按键简易电子琴可自动播放乐曲知识讲解.doc

21按键简易电子琴可自动播放乐曲

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课程设计报告
课程名称：FPGA课程设计 （EDA技术及应用）
题 目：基于FPGA的简易电子琴设计
学 院： 物理与电子工程学院
专 业： 电 子 信 息 工 程
班 级：
学 号：
学生姓名：
指导教师：
起讫日期：

1 设计目的任务及要求 2
设计要求（简易电子琴的功能） 2
1.1 设计目的 2
1.2 设计要求 4
2、设计内容（实现过程） 2
一）、设计思路 1
二）、设计实现 2
1）按键输入的判断 5
A.代码 2
B.波形仿真图 6
2）按键去抖动 6
A.代码 6
B.波形仿真图 7
3）音乐自动播放 7
A.代码 7
B.波形仿真图 9
4）二选一选择器 9
A.代码 9
B.波形仿真图 9
5）按键的输出 10
A.代码 10
B.波形仿真图 11
6）分频预置数的产生 11
A.代码 12
B.波形仿真图 14
7）分频器 14
A.代码 14
B.波形仿真图 16
3、系统仿真与调试 2
4、结束语（感想和心得等） 20
5、主要参考文献 2
基于FPGA的简易电子琴设计
物理与电子工程学院 电子信息工程
1 设计目的任务及要求
1 简易电子琴
1) 设计一个能发出7个音阶的系统并能多种模式播放歌曲（歌曲可自定，至少3首）
2) 利用一基准脉冲产生1，2，3，。。。共7个音阶信号，进行弹奏；
3) 用指示灯显示节拍；
4) *能对弹奏乐曲存储并回放。

1.1设计目的
1、熟悉VHDL语言
2、学习电子琴的设计,调试,仿真以及对仿真波形的调试
1.2设计要求（简易电子琴的功能）
1、设计一个能发出7个音阶的系统并能多种模式播放歌曲（歌曲可自定，至少首）
2、 利用一基准脉冲产生1，2，3，。。。共7个音阶信号，进行弹奏；
3、 用指示灯显示节拍；
4、 *能对弹奏乐曲存储并回放。
2、设计内容
分频预置数ToneTabs
二选一选择器mux21c
自动播放Notetabs

一）、设计思路

分频器SPEAKER

按 键 输 出
SWI
按键去抖动
FEN
按键输入判断ceshi
按 键 输 入

发出音乐
spkout

二）、设计实现
本设计实现了能发出底、中、高三个节拍的7个音阶的系统，整个系统共有3首歌曲，这三首歌曲具有顺序播放和随机切换歌曲的播放功能。能随意弹奏每首歌曲，同时具有数码管显示每个音阶所对应的阿拉伯数字，不同的节拍我们也有相应的指示灯作为区分，在低音时无指示灯亮，中音时有一个亮，高音时有两个指示灯亮。
1）按键输入的判断：
a.代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY ceshi IS
PORT(s: IN STD_LOGIC;
Y:out std_logic);
END ENTITY ceshi;
ARCHITECTURE FUN OF ceshi IS
begin
PROCESS(s)
BEGIN
IF s='1' THEN Y <='1';
ELSE y<='0';
end if;
end process;
END ARCHITECTURE FUN;
b.波形仿真图

2）按键去抖动
a.代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY FEN IS
PORT(CLK,KIN:IN STD_LOGIC;
KOUT:OUT STD_LOGIC);
END;
ARCHITECTURE BHV OF FEN IS
SIGNAL KL,KH:STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS(CLK,KIN,KL,KH) BEGIN
IF CLK'EVENT AND CLK='1' THEN
IF(KIN='0') THEN KL<=KL+1;
ELSE KL<="0000";END IF;
IF(KIN='1') THEN KH<=KH+1;
ELSE KH<="0000";END IF;
IF(KH>"1100") THEN KOUT<='1';
ELSIF(KL>"0111") THEN KOUT<='0';
END IF;
END IF;
END PROCESS;
END;
b.波形仿真图

3）产生节拍控制和音阶选择信号
a.代码
3）音乐自动播放
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY NOTETABS IS
PORT(CLK : IN STD_LOGIC;
S : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
TONEINDEX : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0));
END ENTITY NOTETABS;

ARCHITECTURE FUN OF NOTETABS IS

COMPONENT MUSIC
PORT
(
address : IN STD_LOGIC_VECTOR (8 DOWNTO 0);
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;

SIGNAL COUNTER : STD_LOGIC_VECTOR(8 DOWNTO 0);

BEGIN
PROCESS(CLK,COUNTER)
BEGIN
IF (COUNTER=432) THEN COUNTER<="000000000";
ELSIF (CLK'EVENT AND CLK ='1') THEN COUNTER<= COUNTER+1;
END IF;
IF(S="11" AND COUNTER>144) THEN COUNTER<="000000000";
ELSIF(S="10" AND (COUNTER <144 OR COUNTER>288)) THEN COUNTER<="010010000";
ELSIF (S="01" AND (COUNTER <288 OR COUNTER>432)) THEN COUNTER<="100100000";

ELSE
END IF;
END PROCESS;

U1 : MUSIC PORT MAP(address=>COUNTER,q=>TONEINDEX,clock=>CLK);
END ARCHITECTURE FUN;
b.波形仿真图

4）二选一选择器
a.代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux21c IS
PORT(k_code,toneindex:IN STD_LOGIC_VECTOR(4 DOWNTO 0);
key:IN STD_LOGIC;
index:OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
END;
ARCHITECTURE five OF mux21c IS
BEGIN
PROCESS(k_code,toneindex,key)
BEGIN
IF key='1' THEN index<=k_code;
ELSE index<=toneindex;
END IF;
END PROCESS;
END five;
b.波形仿真图

5）按键的输出
a.代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SWI IS
PORT(A,B,C,D,E,F,G ,H,I,K,L,M,N,O,P,Q,R,S,T,U: IN STD_LOGIC;
Y : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0));
END ENTITY SWI;
ARCHITECTURE FUN OF SWI IS
SIGNAL J : STD_LOGIC_VECTOR( 19 DOWNTO 0);
BEGIN
J<=A&B&C&D&E&F&G&H&I&K&L&M&N&O&P&Q&R&S&T&U;
P1: PROCESS(J)
BEGIN
CASE (J) IS
when "11111111111111111111" => Y<="00000";
WHEN "11111111111111111110" => Y<="00001";
WHEN "11111111111111111101" => Y<="00010";
WHEN "11111111111111111011" => Y<="00011";
WHEN "11111111111111110111" => Y<="00100";
WHEN "11111111111111101111" => Y<="00101";
WHEN "11111111111111011111" => Y<="00110";
WHEN "11111111111110111111" => Y<="00111";
WHEN "11111111111101111111" => Y<="01000";
WHEN "11111111111011111111" => Y<="01001";
WHEN "11111111110111111111" => Y<="01010";
WHEN "11111111101111111111" => Y<="01011";
WHEN "11111111011111111111" => Y<="01100";
WHEN "11111110111111111111" => Y<="01101";
WHEN "11111101111111111111" => Y<="01110";
WHEN "11111011111111111111" => Y<="01111";
WHEN "11110111111111111111" => Y<="10000";
WHEN "11101111111111111111" => Y<="10001";
WHEN "11011111111111111111" => Y<="10010";
WHEN "10111111111111111111" => Y<="10011";
WHEN "01111111111111111111" => Y<="10100";
WHEN OTHERS => NULL;
END CASE;
END PROCESS P1;
END ARCHITECTURE FUN;
b.波形仿真图

6）分频预置数的产生
a.代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY ToneTaba IS
PORT ( Index : IN STD_LOGIC_VECTOR (4 DOWNTO 0);
CODE : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
HIGH1,HIGH2 : OUT STD_LOGIC;
Tone : OUT STD_LOGIC_VECTOR (10 DOWNTO 0));
END;
ARCHITECTURE one OF ToneTaba IS
BEGIN
Search : PROCESS(Index)
BEGIN
CASE Index IS
WHEN "00000" => Tone<="11111111111"; CODE<="0000"; HIGH1 <='0';HIGH2 <='0';
WHEN "00001" => Tone<="01100000101"; CODE<="0001"; HIGH1 <='0';HIGH2 <='0';-- 773;
WHEN "00010" => Tone<="01110010000"; CODE<="0010"; HIGH1 <='0';HIGH2 <='0';-- 912;
WHEN "00011" => Tone<="10000001100"; CODE<="0011"; HIGH1 <='0';HIGH2 <='0';--1036;
when "00100" => Tone<="10001000100"; CODE<="0100"; HIGH1 <='0';HIGH2 <='0';
WHEN "00101" => Tone<="10010101101"; CODE<="0101"; HIGH1 <='0';HIGH2 <='0';--1197;
WHEN "00110" => Tone<="10100001010"; CODE<="0110"; HIGH1 <='0';HIGH2 <='0';--1290;
WHEN "00111" => Tone<="10101011100"; CODE<="0111"; HIGH1 <='0';HIGH2 <='0';--1372;
WHEN "01000" => Tone<="10110000010"; CODE<="0001"; HIGH1 <='1';HIGH2 <='0';--1410;
WHEN "01001" => Tone<="10111001000"; CODE<="0010"; HIGH1 <='1';HIGH2 <='0';--1480;
WHEN "01010" => Tone<="11000000110"; CODE<="0011"; HIGH1 <='1';HIGH2 <='0';--1542;
when "01011" => Tone<="11000100010"; CODE<="0100"; HIGH1 <='1';HIGH2 <='0';
WHEN "01100" => Tone<="11001010110"; CODE<="0101"; HIGH1 <='1';HIGH2 <='0';--1622;
WHEN "01101" => Tone<="11010000100"; CODE<="0110"; HIGH1 <='1';HIGH2 <='0';--1668;
when "01110" => Tone<="11010011010"; CODE<="0111"; HIGH1 <='1';HIGH2 <='0';
WHEN "01111" => Tone<="11011000000"; CODE<="0001"; HIGH1 <='1';HIGH2 <='1';--1728;
WHEN "10000" => Tone<="11011100100"; CODE<="0010"; HIGH1 <='1';HIGH2 <='1';
WHEN "10001" => Tone<="11100000011"; CODE<="0011"; HIGH1 <='1';HIGH2 <='1';
WHEN "10010" => Tone<="11100010001"; CODE<="0100"; HIGH1 <='1';HIGH2 <='1';
WHEN "10011" => Tone<="11100001011"; CODE<="0101"; HIGH1 <='1';HIGH2 <='1';
WHEN "10100" => Tone<="11101000010"; CODE<="0110"; HIGH1 <='1';HIGH2 <='1';
WHEN "10101" => Tone<="11101001100"; CODE<="0111"; HIGH1 <='1';HIGH2 <='1';
WHEN OTHERS => NULL;
END CASE;
END PROCESS;
END;
b.波形仿真图

7）分频器
a.代码
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY SPEAKER IS
PORT(CLK : IN STD_LOGIC;
TONE : IN STD_LOGIC_VECTOR(10 DOWNTO 0);
SPKS : OUT STD_LOGIC);
END ENTITY SPEAKER;

ARCHITECTURE FUN OF SPEAKER IS
SIGNAL PRECLK,FULLSPKS : STD_LOGIC;
BEGIN
PROCESS(CLK)
VARIABLE COUNT4 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PRECLK<='0';
IF COUNT4>11 THEN PRECLK<='1';COUNT4 :="0000";
ELSIF CLK'EVENT AND CLK = '1' THEN COUNT4:=COUNT4+1;
END IF;
END PROCESS;
PROCESS(PRECLK,TONE)
VARIABLE COUNT11 : STD_LOGIC_VECTOR(10 DOWNTO 0);
BEGIN
IF PRECLK'EVENT AND PRECLK ='1' THEN
IF COUNT11 = 16#7FF# THEN COUNT11 := TONE ;FULLSPKS<='1';
ELSE COUNT11 := COUNT11+1;FULLSPKS<='0';
END IF;
END IF;
END PROCESS;
PROCESS(FULLSPKS)
VARIABLE COUNT2 : STD_LOGIC;
BEGIN
IF FULLSPKS'EVENT AND FULLSPKS= '1' THEN COUNT2 := NOT COUNT2;
IF COUNT2 = '1' THEN SPKS<='1';
ELSE SPKS <='0';
END IF;
END IF;
END PROCESS;
END ARCHITECTURE FUN;
b.波形仿真图

3、系统仿真与调试
A、原理图：

B、波形仿真

C、PCB图：

D、调试图：

5、 主要参考文献
[1] 潘松 黄继业 EDA技术实用数据VHDL版（第五版） 科学出版社 2013
[2] 曹昕燕，周凤臣.EDA技术实验与课程设计.清华大学出版社，2006.
[3] 阎石，数学电子技术基础.高等教育出版社，2003.

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