科技英语专题培训市公开课一等奖百校联赛特等奖课件.pptx

外文科技写作与实践 班级：Y120X0X 姓名：XXX 流水号：S20XXXXX第1页FPGA Implementation of Modern Wireless Commuication System第2页FPGA Implementation of Modern Wireless Commuication System题目：题目：当代无线通信系统FPGA实现Abstract:OFDM is considered as an important constituent of modern wireless communication systems because of its capability to provide high data rates,highspectral efficiency and robustness against both inter-symbol and intra-symbol interference.摘要摘要：OFDM含有高数据传输速率、高频率利用率、强抗码间、内部码间干扰能力特点，被认为是当代无线通信系统主要组成部分。第3页 OFDM：(Orthogonal Frequency Division Multiplexing)即正交频分复用技术，是多载波调制一个。其主要思想是：将信道分成若干正交子信道，将高速数据信号转换成并行低速子数据流，调制到在每个子信道上进行传输。正交信号能够经过在接收端采取相关技术来分开，这么能够降低子信道之间相互干扰。每个子信道上信号带宽小于信道相关带宽，所以每个子信道上能够看成平坦性衰落，从而能够消除符号间干扰。而且因为每个子信道带宽仅仅是原信道带宽一小部分，信道均衡变得相对轻易。第4页Abstract：OFDM inherently perform its operations in parallel fashion,so it is vital that any implem-entation should execute OFDMs operation in p-arallel by default.This paper is focused on imp-lementing different OFDM modules on modern FPGA devices.摘要摘要：OFDM工作方式为并行，所以任何实现方式须以并行方式执行。本文叙述了不一样OFDM模块在FPGA上实现。Keywords:OFDM,FPGA,Altera,DSP Builder,Cyclon devices关键字：关键字：OFDM,FPGA,Altera,DSP Builder，Cyclon devices第5页一些名词inter-symbol 码间intra-symbol 内部码间parallel fashion/mode 并行方式serial mode 串行方式Convolutional Encoder 卷积编码器Block interleaver 块分组交织器QAM Mapper 正交幅度调制映射simulation 仿真implemetation 实现Viterbi Decoder 维特比译码器第6页 交织器通常是对输入原始信息序列进行随机置换后从前向后读出。交织器作用是：一、能够产生长码。二、使两个编码器输入不相关，编码过程趋于独立。交织使编码产生随机度，使码随机化、均匀化，起着对码重量整形作用，直接影响码性能。交织方式主要有规则交织，不规则交织和随机交织3种。通常规则交织即行写列读，效果不好。随机交织指交织格式是随机分配，是理论上性能最好交织方式，不过因为要将整个交织信息位置信息传送给译码器，降低了编码效率。实际应用中普通采取不规则交织，这是一个伪随机交织方式，对每一编码块采取固定交织方式，但块与块之间交织器结构不一样。往往为了取得高编码增益对交织器长度提出要求。在无线移动通信系统对时延要求较高，所以采取交织长度为400左右伪随机短交织器。第7页Conclusion Different components of OFDM systen were using Altera DSP Builder Technology in the Simulink environ-ment.All the simulations were done successfully in this industry-standard MATLAB environment,and then the D-SP signal compiler was used for compilation,synthesis and design fitting.结论结论：OFDM系统不一样组件都能够使用Altera企业 DSP Builder技术进行仿真。首先，在Matlab环境下进行仿真，成功实现后，再使用DSP信号编译器进行编译，综合和设计拟合。第8页Conclusion After these steps all the modules were independently implemented on Altera Cyclone chips.Outputs were shown on the physical deivce and verified and compared with simulation(and litereature)results.结论：结论：经过这些步骤，将全部模块独立在Altera企业Cyclone芯片上运行。将输出显示在物理设备，经过验证，而且与仿真结果进行比较。第9页Conclusion In short Altera Cyclone chips can easily be used for implementation of different modules of OFDM system and of course the FPGA designs are flexble enough to b-e given priority over both ASIC and microcontroller-based design.结论：结论：总之，OFDM系统不一样模块能够在Altera企业Cyclone芯片很轻易实现，而且与ASIC和基于微控制器设计相比，FPGA还含有设计灵活性，所以无线通信FPGA实现含有非常现实意义。第10页Future work This piece of work can be extended in future by impl-ementing transmitter and receiver on separate chips and then sending and receving the data independently and fin-ally one can analyse different things like effect of channel and maximum achievable data rates.If one succeeds in im-plementing transmitter and receiver separately,then re-sults can be compared with conventional implemetation techiqu-es and can investigate the difference.这项工作能够扩展到在不一样芯片上发射和接收，发送和接收数据独立，能够分析不一样通道数影响和可到达最大数据速率。一旦这项研究成功，将结果与用传统方法得到结果进行对比，比较二者不一样。第11页Ackonwledgement第12页FPGA Based High Speed BCH Encoder for Wireless Communication Application第13页FPGA Based High Speed BCH Encoder for Wireless Communication Application题目：题目：基于高速BCH编码器FPGA在无线通信中应用 BCH码是一类主要纠错码，它把信源待发信息序列按固定位一组划分成消息组,再将每一消息组独立变换成长为n(n)二进制数字组,称为码字。假如消息组数目为M(显然M2),由此所取得M个码字全体便称为码长为n、信息数目为M分组码,记为n，M。把消息组变换成码字过程称为编码，其逆过程称为译码。第14页Abstract This paper presents prototyping of a high speed and area efficient BCH encoder on an FPGA target device for wireless communication applications.FPGA implemetai-on is very fast,easy to modify and suitable for prototyping products.本文介绍了一个应用于无线通信技术基于BCH编码器FPGA器件。FPGA含有快速实现、易于修改、适合原型器件特点。第15页Abstract BCH encoder is usually implemented with linear fe-edback shift register architecture.BCH codes can be de-fined by two parameters that are numbers of errors to be corrected and code size.The proposed BCH encoder h-as been developed and simulated using MATLAB along with Xinlinx DSP Tools,synthesized with XST and imple-mented on Spartan 3E target FPGA device.BCH编码器通常应用于线性反馈移位存放器。BCH码有两个参数，分别对误差进行修正和对代码尺寸数字定义。提及BCH编码器已使用MATLAB和Xilinx企业 DSP工具进行了仿真，与XST合成并应用于Spartan 3E FPGA器件上。第16页Abstract The results show that proposed BCH encoder can opreate at a maximum frequency of 249.8 MHZ by con-suming negligible resources of target device.结果表明，提出BCH编码器在忽略其它资源情况下，运行时能够到达最大频率为249.8兆赫 Keywords:ARQ,BCH encoding,CRT,FEC,LFSR关键词关键词：自动重复请求，BCH编码器，阴极射线管,前向纠错，线性反馈移位存放器第17页Conclusion In this paper,high speed design of BCH encoder is proposed for wireless communication based systems.The proposed design has shown an efficient realization of BCH encoder by using embedded LUTs of target FP-GA to provide high speed operation.The results have b-een verifided through Xilinx DSP Tool simulation and te-sting.在本文中，提出了将高速BCH编码器用于无线通信系统。该设计经过使用FPGA器件嵌入LUTS成功实现BCH编码器。结果已经经过Xilinx DSP仿真和测试工具进行了验证。第18页Conclusion The proposed BCH Encoder has been implemented on Spartan 3E based xc3s500e target device using fully parallel LUT based mu-ltiplier less technique.The results show that proposed design can w-ork at an estimated fre-quency of 249.8MHz by using negligible res-ources of target FPGA to provide cost effective solution for wirele-ss communication systems.提出BCH编码器已经在基于XC3S500E器件Spar-tan 3E上采取完全并行LUT乘数算法实现。结果表明，所提出设计在249.8mhz频率下工作仅使用FPGA极少资源，而且成本很低，对无线通信技术发展含有可观意义。第19页Ackonwledgement第20页谢谢大家！第21页