veriloghdl电子琴专业课程设计.doc

湖北文理学院

课程设计汇报

题 目 Verilog hdl课程设计
专 业 1211自动化
学生姓名 一天虹影
指导老师 单鸣雷
完成时间 —1—9

课程设计（汇报）任务书
（理 工 科 类）
课程设计（汇报）题目：
电子琴设计
课程设计（论文）工作内容
一、课程设计目标
1、培养综合利用知识和独立开展实践创新能力；
2、深入学习Verilog HDL，了解其编程环境；
3、学会利用Modelsim和Quartus II等编程仿真软件；
4、将硬件语言编程和硬件实物功效演示相结合，加深了解Verilog HDL学习；
二、研究方法及手段应用
1、将任务分成若干模块，查阅相关论文资料，分模块调试和完成任务；
2、碰到问题小组组员立即讨论得出处理方法；
3、碰到本组内处理不了问题，立即和其它小组交流或问询老师；
4、程序仿真，仿真无问题后进行模块调试，依据试验箱上硬件实现是否符合要求来检验程序正确是否。
三、课程设计预期效果
1、完成试验环境搭建；
2、含有手动弹奏和自动播放功效；
3、以按键（或开关）作为琴键，最少能够经过蜂鸣器输出7个音阶；
4、自动播放曲目最少两首；

摘 要

简易电子琴设计经过经过软硬件结合实现，硬件系统包含主控器芯片、9个按键、LED、蜂鸣器等，软件资源包含编写Verilog HDL程序应用软件Modelsim和仿真软件Quartus II。电子琴有按键替换琴键弹奏功效和自动播放功效。按键有七个音，自动播放功效中有三首曲子，分别是《两只老虎》、《天空之城》和《康定情歌》。程序共有五个模块，分别为主模块、琴键模块、曲1模块、曲2模块、曲3模块。硬件实现是用三个LED灯组合亮暗分别表示七个按键按下情况，另外两个按键用来选择曲目。试验箱原始时钟为50MHz，分频后变成不一样频率输出，经过蜂鸣器输出不一样频率声音。音乐节拍经过分频变为4Hz，作为1/4拍。经过主模块调用各模块实现电子琴功效。

【关键词】Verilog HDL 电子琴 模块 分频
ABSTRACT
This article introduced the simple electric piano’s design. It realizes through the software and hardware union. The hardware system includes a director, 9 keys, LEDs and a buzzer. The software design uses Verilog HDL. Emulation uses Quartus II. It can broadcast the system establishment the corresponding note, and can complete a military song the broadcast, but also has shows the sound the function. Designs the simple electric piano to have in the hardware. The program has seven modules, including main module, fractional frequency module and so on. Keyboard with keys to play the function and replace the keys to play function. Key has seven sound, automatic playback function with three in song, were the two tiger ", "the sky city" and "kangding love songs. Software has its merit. It is perfect in the software Verilog HDL. The original frequency is divided into different frequencys. The piano makes sound by the buzzer with different frequencys.

【keywords】Verilog HDL electric piano module fractional frequency

第一章 系统设计

第一节 课题目标及总体方案

此次项目设计课程目标是让我们在学习Verilog HDL基础上愈加深入了解硬件设计语言功效、作用及其特征，而且将我们动手能力和创新能力结合起来。此次电子琴试验目标是：
1、含有手动弹奏和自动播放功效；
2、以按键（或开关）作为琴键，最少能够经过蜂鸣器输出7个音阶；
3、自动播放曲目最少两首；
此次试验方框图为：（每个模块中全部有分频）
主模块
九个键
Key1到Key7用于弹奏
Key8和Key9（mm）用于选择歌曲
mm=00
按键模块
Key1
到
Key7
模块名digital_piano
mm=01
曲目1《两只老虎》
模块名 bell
mm=10
曲目2《康定情歌》
模块名 bell2
mm=11
曲目3《天空之城》
模块名 bell3

第二节 设计框图说明

一、 主模块
主模块中用mm=(key8,key9)值不一样选择调用不一样模块，mm=01调用曲目1模块，即bell模块；mm=10调用曲目2模块，即bell2模块；mm=11调用曲目3模块，即bell3模块；而在key8和key9没有被按下情况下，程序调用按键模块，即digital_piano模块
module main(inclk,outclk,key1,key2,key3,key4,key5,key6,key7,key8,key9,num);
input inclk;
input key1,key2,key3,key4,key5,key6,key7,key8,key9;
output outclk;
output[3:0]num;
reg outclk,clk_6M;
reg [3:0]c;
wire out1,out2,out3,out4;
wire[8:0] key;
reg [1:0]mm;
assign key = {key1,key2,key3,key4,key5,key6,key7,key8,key9}; //由按键拼键为变量key
//调用子调块
digital_piano m1(.inclk(inclk),.key1(key1),.key2(key2),.key3(key3),.key4(key4),
.key5(key5),.key6(key6),.key7(key7),.beep2(out2),.num(num));
bell m2(.inclk(inclk),.beep1(out1));
bell2 m3(.inclk(inclk),.beep3(out3));
bell3 m4(.inclk(inclk),.beep4(out4));

always @(posedge clk_6M) //在时钟上升沿检测是否有按键按下
begin
if(key == 9'b)
mm <= 2'b01;
else if(key==9'b)
mm <= 2'b10;
else if(key==9'b)
mm <= 2'b11;
else mm <= 2'b00;
end
always@(posedge inclk)
begin
if(c<4'd4)
c<=c+4'd1;
else
begin
c<=4'd0;
clk_6M=~clk_6M;
end
end

always @(posedge clk_6M)
begin
if(mm == 2'b01)
outclk <= out1;
else if(mm == 2'b00)
outclk <= out2;
else if(mm == 2'b10)
outclk <= out3;
else outclk <= out4;
end
endmodule

二、按键模块
Key1到key7对应do到si七个音，用于模拟电子琴弹奏
//digital_piano子模块
module digital_piano(inclk,key1,key2,key3,key4,key5,key6,key7,beep2,num);
input inclk,key1,key2,key3,key4,key5,key6,key7;
output[3:0]num;
output beep2;
wire [6:0] key_code;
reg [3:0]c;
reg clk_6M;
reg beep_r;
reg [3:0]num;
reg [15:0] count;
reg [15:0] count_end;
parameter Do = 7'b1111110, //状态机7个编码，分别对应中音7个音符
re = 7'b1111101,
mi = 7'b1111011,
fa = 7'b1110111,
so = 7'b1101111,
la = 7'b1011111,
si = 7'b0111111;
assign key_code = {key7,key6,key5,key4,key3,key2,key1};
assign beep2 = beep_r; //输出音乐

always@(posedge inclk)
begin
if(c<4'd4)
c<=c+4'd1;
else
begin
c<=4'd0;
clk_6M=~clk_6M;
end
end

always@(posedge clk_6M) //分频模块，得出乐谱
begin
count <= count + 16'd1; //计数器加1
if(count == count_end)
begin
count <=16'd0; //计数器清零
beep_r <= !beep_r;
end
end

always@(posedge clk_6M) //状态机，依据按键状态，选择不一样音符输出
begin
case(key_code)
Do: count_end <= 16'd11450;
re: count_end <= 16'd10204;
mi: count_end <= 16'd09090;
fa: count_end <= 16'd08571;
so: count_end <= 16'd07802;
la: count_end <= 16'd06802;
si: count_end <= 16'd06060;
default:count_end <= 16'd0;
endcase
end

always @ (posedge clk_6M)
begin
case(key_code)
Do: num<=4'b0001;
re: num<=4'b0010;
mi: num<=4'b0011;
fa: num<=4'b0100;
so: num<=4'b0101;
la: num<=4'b0110;
si: num<=4'b0111;
endcase
end
endmodule

二、 曲目1模块
//bell子模块 《两只老虎》
module bell (inclk,beep1);
input inclk; //系统时钟
output beep1; //蜂鸣器输出端
reg [3:0]high,med,low;
reg [15:0]origin;
reg beep_r; //寄存器
reg [7:0]state;
reg [15:0]count;
assign beep1=beep_r; //输出音乐

//时钟频率6MHz
reg clk_6MHz;
reg [2:0] cnt1;
always@(posedge inclk)
begin
if(cnt1<3'd4)
cnt1<=cnt1+3'b1;
else
begin
cnt1<=3'b0;
clk_6MHz<=~clk_6MHz;
end
end
//时钟频率4MHz
reg clk_4Hz;
reg [24:0] cnt2;
always@(posedge inclk)
begin
if(cnt2<25'd6250000)
cnt2<=cnt2+25'b1;
else
begin
cnt2<=25'b0;
clk_4Hz<=~clk_4Hz;
end
end

always @(posedge clk_6MHz)
begin
count <= count + 1'b1; //计数器加1
if(count == origin)
begin
count <= 16'h0; //计数器清零
beep_r <= !beep_r; //输出取反
end
end

always@(posedge clk_4Hz)
begin
case({high,med,low})
12'b:origin=11466;//mid1
12'b:origin=10216;//mid2
12'b:origin=9101;//mid3
12'b:origin=8590;//mid4
12'b:origin=7653;//mid5
12'b:origin=6818;//mid6
12'b:origin=14447;//low5
endcase
end

always @(posedge clk_4Hz) //歌曲 <<two tiger>>
begin
if(state ==63) state = 0;//计时，以实现循环演奏
else
state = state + 1;
case(state)
0,1: {high,med,low}=12'b;//mid1
2,3: {high,med,low}=12'b;//mid2
4,5: {high,med,low}=12'b;//mid3
6,7: {high,med,low}=12'b;//mid1

8,9: {high,med,low}=12'b;//mid1
10,11: {high,med,low}=12'b;//mid2
12,13: {high,med,low}=12'b;//mid3
14,15: {high,med,low}=12'b;//mid1

16,17: {high,med,low}=12'b;//mid3
18,19: {high,med,low}=12'b;//mid4
20,21,22,23: {high,med,low}=12'b;//mid5

24,25: {high,med,low}=12'b;//mid3
26,27: {high,med,low}=12'b;//mid4
28,29,30,31: {high,med,low}=12'b;//mid5

32: {high,med,low}=12'b;//mid5
33: {high,med,low}=12'b;//mid6
34: {high,med,low}=12'b;//mid5
35: {high,med,low}=12'b;//mid4
36,37: {high,med,low}=12'b;//mid3
38,39: {high,med,low}=12'b;//mid1

40: {high,med,low}=12'b;//mid5
41: {high,med,low}=12'b;//mid6
42: {high,med,low}=12'b;//mid5
43: {high,med,low}=12'b;//mid4
44,45: {high,med,low}=12'b;//mid3
46,47: {high,med,low}=12'b;//mid1

48,49: {high,med,low}=12'b;//mid2
50,51: {high,med,low}=12'b;//low5
52,53,54,55: {high,med,low}=12'b;//mid1

56,56: {high,med,low}=12'b;//mid2
57,58: {high,med,low}=12'b;//low5
59,60,61,62,63: {high,med,low}=12'b;//mid1
default : {high,med,low}=12'bx;
endcase
end
endmodule

三、 曲目2模块
//bell2子模块《康定情歌》
module bell2 (inclk,beep3);
input inclk; //系统时钟
output beep3; //蜂鸣器输出端
reg [3:0]high,med,low;
reg [15:0]origin;
reg beep_r; //寄存器
reg [7:0]state;
reg [15:0]count;
assign beep3=beep_r; //输出音乐

//时钟频率6MHz
reg clk_6MHz;
reg [2:0] cnt1;
always@(posedge inclk)
begin
if(cnt1<3'd4)
cnt1<=cnt1+3'b1;
else
begin
cnt1<=3'b0;
clk_6MHz<=~clk_6MHz;
end
end
//时钟频率4MHz
reg clk_4Hz;
reg [24:0] cnt2;
always@(posedge inclk)
begin
if(cnt2<25'd6250000)
cnt2<=cnt2+25'b1;
else
begin
cnt2<=25'b0;
clk_4Hz<=~clk_4Hz;
end
end

always @(posedge clk_6MHz)
begin
count <= count + 1'b1; //计数器加1
if(count == origin)
begin
count <= 16'h0; //计数器清零
beep_r <= !beep_r; //输出取反
end
end
always@(posedge clk_4Hz)
begin
case({high,med,low})
'b:origin=22900; //低1
'b:origin=20408; //低2
'b:origin=18181; //低3
'b:origin=15267; //低5
'b:origin=13605; //低6
'b:origin=11472; //中1
'b:origin=10216; //中2
'b:origin=9101; //中3
'b:origin=7653; //中5
'b:origin=6818; //中6
'b:origin=5733; //高1
'b:origin=5108; //高2
'b:origin=4551; //高3
endcase
end
always @(posedge clk_4Hz)
begin
if(state ==103)
state = 0;
else
state = state + 1; //《康定情歌》
case(state)
0,1: {high,med,low}='b;//中3
2,3: {high,med,low}='b;//中5
4,5: {high,med,low}='b;//中6
6: {high,med,low}='b;//中6
7: {high,med,low}='b;//中5
8,9,10: {high,med,low}='b;//中6
11: {high,med,low}='b;//中3
12,13,14,15: {high,med,low}='b;//中2
16,17: {high,med,low}='b;//中3
18,19: {high,med,low}='b;//中5
20,21: {high,med,low}='b;//中6
22: {high,med,low}='b;//中6
23: {high,med,low}='b;//中5
24,25: {high,med,low}='b;//中6
26,27,28,29,30,31:{high,med,low}='b;//中3
32,33: {high,med,low}='b;//中3
34,35: {high,med,low}='b;//中5
36,37: {high,med,low}='b;//中6
38: {high,med,low}='b;//中6
39: {high,med,low}='b;//中5
40,41,42: {high,med,low}='b;//中6
43: {high,med,low}='b;//中3
44,45,46,47: {high,med,low}='b;//中2
48,49: {high,med,low}='b;//中5
50,51: {high,med,low}='b;//中3
52: {high,med,low}='b;//中2
53: {high,med,low}='b;//中3
54: {high,med,low}='b;//中2
55: {high,med,low}='b;//1
56,57: {high,med,low}='b;//中2
58,59,60,61,62,63:{high,med,low}='b;//低6
64,65: {high,med,low}='b;//中6
66,67,68,69,70,71:{high,med,low}='b;//中2
72,73: {high,med,low}='b;//中5
74,75,76,77,78,79:{high,med,low}='b;//中3
80: {high,med,low}='b;//中2
81: {high,med,low}='b;//1
82,83,84,85,86,87:{high,med,low}='b;//中6
88,89: {high,med,low}='b;//中5
90,91: {high,med,low}='b;//中3
92: {high,med,low}='b;//中2
93: {high,med,low}='b;//中3
94: {high,med,low}='b;//中2
95: {high,med,low}='b;//1
96,97: {high,med,low}='b;//中2
98,99,100,101,102,103:{high,med,low}='b;//中6
endcase
end
endmodule

四、 曲目3模块
//bell3子模块《天空之城》
module bell3 (inclk,beep4);
input inclk; //系统时钟
output beep4; //蜂鸣器输出端
reg [3:0]high,med,low;
reg [15:0]origin;
reg beep_r; //寄存器
reg [7:0]state;
reg [15:0]count;
assign beep4=beep_r; //输出音乐

//时钟频率6MHz
reg clk_6MHz;
reg [2:0] cnt1;
always@(posedge inclk)
begin
if(cnt1<3'd4)
cnt1<=cnt1+3'b1;
else
begin
cnt1<=3'b0;
clk_6MHz<=~clk_6MHz;
end
end
//时钟频率4MHz
reg clk_4Hz;
reg [24:0] cnt2;
always@(posedge inclk)
begin
if(cnt2<25'd6250000)
cnt2<=cnt2+25'b1;
else
begin
cnt2<=25'b0;
clk_4Hz<=~clk_4Hz;
end
end

always @(posedge clk_6MHz)
begin
count <= count + 1'b1; //计数器加1
if(count == origin)
begin
count <= 16'h0; //计数器清零
beep_r <= !beep_r; //输出取反
end
end
always@(posedge clk_4Hz)
begin
case({high,med,low})
'b:origin=22900; //低1
'b:origin=20408; //低2
'b:origin=18181; //低3
'b:origin=17142; //低4
'b:origin=15267; //低5
'b:origin=13605; //低6
'b:origin=12121; //低7
'b:origin=11472; //中1
'b:origin=10216; //中2
'b:origin=9101; //中3
'b:origin=8571; //中4
'b:origin=7653; //中5
'b:origin=6818; //中6
'b:origin=6060; //中7
'b:origin=5733; //高1
'b:origin=5108; //高2
'b:origin=4551; //高3
'b:origin=4294; //高4
'b:origin=3826; //高5
'b:origin=3409; //高6
'b:origin=3050; //高7
endcase
end
always @(posedge clk_4Hz)
begin
if(state ==195)state = 0;
else
state = state + 1; //kang ding qing ge
case(state)
0: {high,med,low}='b;//中6
1: {high,med,low}='b;//中7
2,3,4: {high,med,low}='b;//高1
5: {high,med,low}='b;//中7
6,7: {high,med,low}='b;//高1
8,9: {high,med,low}='b;//高3
10,11,12,13,14,15:
{high,med,low}='b;//中7
16,17: {high,med,low}='b;//中3
18,19,20: {high,med,low}='b;//中6
21: {high,med,low}='b;//中5
22,23: {high,med,low}='b;//中6
24,25: {high,med,low}='b;//中1
26,27,28,29,30,31:
{high,med,low}='b;//中5
32: {high,med,low}='b;//中3
33: {high,med,low}='b;//中3

34,35,36: {high,med,low}='b;//中4
37: {high,med,low}='b;//中3
38: {high,med,low}='b;//中4
39,40,41: {high,med,low}='b;//高1
42,43,44: {high,med,low}='b;//中3
45,46,47: {high,med,low}='b;//高1
48,49,50: {high,med,low}='b;//中7
51,52,53: {high,med,low}='b;//中4
54,55,56,57,58,59,60,61:
{high,med,low}='b;//中7
62: {high,med,low}='b;//中6
63: {high,med,low}='b;//中7

64,65,66: {high,med,low}='b;//高1
67: {high,med,low}='b;//高7
68,69: {high,med,low}='b;//高1
70,71: {high,med,low}='b;//高3
72,73,74: {high,med,low}='b;//中7
75,76: {high,med,low}='b;//中3
77,78,79: {high,med,low}='b;//中6
80: {high,med,low}='b;//中5
81,82: {high,med,low}='b;//中6
83,84: {high,med,low}='b;//中1
85,86,87,88,89,90:
{high,m