FPGA设计时序收敛.ppt

单击此处编辑母版文本样式,第二级,第三级,*,*,TJPU-Xilinx Signal Transmission&Processing Joint Lab,天津工业大学-Xilinx信号传输与处理联合实验室,单击此处编辑母版标题样式,*,*,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,*,FPGA设计时序收敛,FPGA设计时序收敛FPGA设计时序收敛提高设计的工作频率,通过附加约束可以控制逻辑的综合、映射、布局和布线，以减小逻辑和布线延时，从而提高工作频率。,获得正确的时序分析报告,FPGA设计平台包含静态时序分析工具，可以获得映射或布局布线后的时序分析报告，从而对设计的性能做出评估。,静态时序分析工具以约束作为判断时序是否满足设计要求的标准。,指定FPGA引脚位置与电气标准,FPGA的可编程特性使电路板设计加工和FPGA设计可以同时进行，而不必等FPGA引脚位置完全确定，从而节省了系统开发时间。,通过约束还可以指定I/O引脚所支持的接口标准和其他电气特性。附加约束的基本作用3/22/20212,人有了知识，就会具备各种分析能力，明辨是非的能力。,提高设计的工作频率,通过附加约束可以控制逻辑的综合、映射、布局和布线，以减小逻辑和布线延时，从而提高工作频率。,获得正确的时序分析报告,FPGA设计平台包含静态时序分析工具，可以获得映射或布局布线后的时序分析报告，从而对设计的性能做出评估。,静态时序分析工具以约束作为判断时序是否满足设计要求的标准。,指定FPGA引脚位置与电气标准,FPGA的可编程特性使电路板设计加工和FPGA设计可以同时进行，而不必等FPGA引脚位置完全确定，从而节省了系统开发时间。,通过约束还可以指定I/O引脚所支持的接口标准和其他电气特性。,附加约束的基本作用,10/17/2026,2,周期(PERIOD)指参考网络为时钟的同步元件间的路径，包括：flip-flop、latch、synchronous RAM等。,周期约束不会优化以下路径,：,从输入管脚到输出管脚之间的路径纯组合逻辑,从输入管脚到同步元件之间的路径,从同步元件到输出管脚的路径,周期约束路径示意图,周期约束,10/17/2026,3,周期约束是一个基本时序和综合约束，它附加在时钟网线上，时序分析工具根据周期约束检查与同步时序约束端口（指有建立、保持时间要求的端口）相连接的所有路径延迟是否满足要求（不包括PAD到寄存器的路径）。,周期是时序中最简单也是最重要的含义，其它很多时序概念会因为软件商不同略有差异，而周期的概念却是最通用的，周期的概念是FPGA/ASIC时序定义的基础概念。后面要讲到的其它时序约束都是建立在周期约束的基础上的，很多其它时序公式，可以用周期公式推导。,在附加周期约束之前，首先要对电路的时钟周期有一定的估计，不能盲目上。约束过松，性能达不到要求，约束过紧，会大大增加布局布线时间，甚至效果相反。,周期约束,10/17/2026,4,周期约束的计算,设计内部电路所能达到的,最高运行频率,取决于同步元件本身的建立保持时间，以及同步元件之间的逻辑和布线延迟。,时钟的最小周期为：,Tperiod=Tcko+Tlogic+Tnet+Tsetup-Tclk_skew,Tclk_skew=Tcd1-Tcd2,其中,Tcko,为时钟输出时间，,Tlogic,为同步元件之间的组合逻辑延迟，,Tnet,为网线延迟，,Tsetup,为同步元件的建立时间，,Tclk_skew,为时钟信号偏斜。,周期约束,10/17/2026,5,附加周期约束的一个例子：,NET SYS_CLK PERIOD=10ns HIGH 4ns,这个约束将被附加到SYS_CLK所驱动的所有同步元件上。,PERIOD约束自动处理寄存器时钟端的反相问题，如果相邻同步元件时钟相位相反，那么它们之间的延迟将被默认限制为PERIOD约束值的一半。,反相时钟周期约束问题的例子,周期约束,10/17/2026,6,偏移约束指,数据和时钟之间,的约束，偏移约束规定了外部时钟和数据输入输出引脚之间的时序关系，,只用于与PAD相连的信号,，不能用于内部信号。,偏移约束示意图,偏移约束,10/17/2026,7,偏移约束优化以下时延路径,从输入管脚到同步元件,偏置输入,(OFFSET IN),从同步元件到输出管脚,偏置输出,(OFFSET OUT),为了确保芯片数据采样可靠和下级芯片之间正确的交换数据，需要约束外部时钟和数据输入输出引脚之间的时序关系。偏移约束的内容的时刻，从而保证与下一级电路的时序关系。告诉综合器、布线器输入数据到达的时刻，或者输出数据稳定,。,偏移约束,10/17/2026,8,OFFSET_IN_BEFORE,说明了输入数据比有效时钟沿提前多长时间准备好，于是芯片内部与输入引脚的组合逻辑延迟就不能大于该时间,（,上限,最大值,），,否则将发生采样错误。,OFFSET_IN_AFTER,指出输入数据在有效时钟沿之后多长时间到达芯片的输入引脚，也可以得到芯片内部延迟的上限。,偏移约束,10/17/2026,9,输入到达时间计算时序描述,OFFSET_IN_AFTER定义的含义是输入数据在有效时钟沿之后的,Tarrival,时刻到达。即：,Tarrival=Tcko+Toutput+Tlogic,综合实现工具将努力使输入端延迟,Tinput 满足以下关系：,Tarrival+Tinput+TsetupTperiod,其中,Tinput,为输入端的组合逻辑、网线和PAD的延迟之和，,Tsetup,为输入同步元件的建立时间,Tcko,为同步元件时钟输出时间。,偏移约束,10/17/2026,10,例子,：假设,Tperiod,=20ns，,Tcko,1ns，,Toutput,3ns，,Tlogic,8ns，请给出偏移约束。,偏移约束,Tarrival=Tcko+Toutput+Tlogic,12ns,，,使用,OFFSET_IN_AFTER,进行偏移约束为：,NET DATA_IN OFFSET=IN 12ns AFTER CLK,也可以使用,OFFSET_IN_BEFORE,进行偏移约束，它们是等价的：,NET DATA_IN OFFSET=IN 8ns BEFORE CLK,10/17/2026,11,OFFSET_OUT_BEFORE,指出下一级芯片的输入数据应该在,有效时钟沿之前多长时间,准备好。,从下一级的输入端的延迟可以计算出当前设计输出的数据必须在何时稳定下来，根据这个数据对设计输出端的逻辑布线进行约束，以满足下一级的建立时间要求，保证下一级采样数据稳定。,OFFSET_OUT_AFTER,规定了输出数据在有效时钟沿之后多长时间,(,上限，最大值,),稳定下来，芯片内部的输出延迟必须小于这个值。,偏移约束,10/17/2026,12,计算要求的输出稳定时间,定义：,Tstable=Tlogic+Tinput+Tsetup,只要当前设计输出端的数据比时钟上升沿提前,Tstable,时间稳定下来，下一级就可以正确采样数据。,实现工具将会努力使输出端的延迟,满足以下关系：,Tcko+Toutput+TstableTperiod,这个公式就是,Tstable,必须要满足的基本时序关系，即本级的输出应该保持怎么样的稳定状态，才能保证下级芯片的采样稳定。,偏移约束,10/17/2026,13,例子：,设时钟周期为20ns，后级输入逻辑延时,Tinput,为4ns、建立时间,Tsetup,为1ns，中间逻辑,Tlogic,的延时为8ns，请给出设计的输出偏移约束。,答案：,OFFSET_OUT_BEFORE 偏移约束为：,NET DATA_OUT OFFSET=OUT 13ns BEFORE CLK,OFFSET_OUT_AFTER约束：,NET DATA_OUT FFSET=OUT 7ns AFTER CLK,偏移约束,10/17/2026,14,Given the system diagram below,what values would you put in the Constraints Editor so that the system will run at,100 MHz,?（,Assume no clock skew between devices）,4 ns,5 ns,Upstream Device,Downstream Device,偏移约束,10/17/2026,15,Path-Specific Timing Constraints,Using global timing constraints(PERIOD,OFFSET,and PAD-TO-PAD)will constrain your entire design,Using only global constraints often leads to over-constrained designs,Constraints are too tight,Increases compile time and can prevent timing objectives from being met,Review performance estimates provided by your synthesis tool or the Post-Map Static Timing Report,Path-specific constraints override the global constraints on specified paths,This allows you to loosen the timing requirements on specific paths,10/17/2026,16,Areas of your design that can benefit from path-specific constraints,Multi-cycle paths,Paths that cross between clock domains,Bidirectional buses,I/O timing,Path-specific timing constraints should be used to define your performance objectives and should not be indiscriminately placed,Path-Specific Timing Constraints,10/17/2026,17,Path-Specific Timing Constraints,10/17/2026,18,Path-Specific Timing Constraints,10/17/2026,19,假设要做一个32位的高速计数器，由于计数器的速度取决于最低位到最高位的进位延迟，为了提高速度采用了预定标计数器的结构，也就是把计数器分成一个小计数器和一个大计数器，如图所示。,其中小计数器是两位的，大计数器是30位，它们由同一时钟驱动。大计数器使能端EN受小计数器进位驱动，小计数器每4个CLK进位一次，使EN持续有效一个CLK的时间，此时有效时钟沿到来大计数器加1。,可见，小计数器的寄存器可能每个CLK翻转1次，低位寄存器输出的数据必须在1个CLK内到达高位寄存器的输入端，即寄存器之间的最大延时为1个CLK。而大计数器内部的寄存器每4个时钟周期才可能翻转一次，低位寄存器输出的数据在4个CLK内到达高位寄存器的输入端即可，即寄存器之间的最大延迟为4个CLK，因此降低了计数器的时序要求，可以实现规模较大的高速计数器。,预定标计数器,Path-Specific Timing Constraints,10/17/2026,20,约束文件,Path-Specific Timing Constraints,10/17/2026,21,Use the Pad to Setup and Clock to Pad columns to specify OFFSETs for all I/O paths on each clock domain.Easiest way to constrain most I/O paths,However,this can lead to an over-constrained design,Use the Pad to Setup and Clock to Pad columns to specify OFFSETs for each I/O pin,Use this type of constraint when only a few I/O pins need different timing,Path-pin offset Timing Constraints,10/17/2026,22,False paths Constraints,If a PERIOD constraint were placed on this design,what delay paths would be constrained?,If the goal is to optimize the input and output times without constraining the paths between registers,what constraints are needed?,Assume that a global PERIOD constraint is already defined,10/17/2026,23,Timing Constraint Priority,False paths,Must be allowed to override any timing constraint,FROM THRU TO,FROM TO,Pin-specific OFFSETs,Group OFFSETs,Groups of pads or registers,Global PERIOD and OFFSETs,Lowest priority constraints,10/17/2026,24,主要内容,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分析,时序收敛流程实现技术,时序收敛流程,FloorPlanner,和,PACE,10/17/2026,25,设计完成后，如何判断一个成功的设计？,设计是否满足,面积要求,-是否能在选定的器件中实现。,设计是否满足,性能要求,-能否达到要求的工作频率。,管脚定义,是否满足要求-信号名、位置、电平标准及数据 流方向等。,时序收敛流程,10/17/2026,26,如何判断设计适合所选芯片？,所选芯片是否有足够的资源容纳更多的逻辑？如果有，有多少？,如果适合所选芯片,能否完全成功布通?,手段：查看,Map Report,或者,Place&Route Report,时序收敛流程,10/17/2026,27,Project Navigator,产生两种时序报告：,Post-Map Static Timing Report,Post-Place&Route Static Timing Report,时序报告包含没有满足时序要求的详细路径的描述，用于分析判断时序要求没有得到满足的原因。,Timing Analyzer,用于建立和阅读时序报告。,时序收敛流程,10/17/2026,28,合理的性能约束的依据,Post-Map Static Timing Report,包括：实际的,逻辑延迟,和(block delays)和,0.1 ns网络延迟,(net delays),合理的时序性能约束的原则：60/40 原则,If less than 60 percent of the timing budget is used for logic delays,the Place&Route tools should be able to meet the constraint easily.,Between 60 to 80 percent,the software run time will increase.,Greater than 80 percent,the tools may have trouble meeting your goals.,时序收敛流程,10/17/2026,29,时序收敛流程,10/17/2026,30,性能突破只要三步：,1.,充分利用嵌入式（专用）资源,DSP48,PowerPC processor,EMAC,MGT,FIFO,block RAM,ISERDES,and OSERDES,等等。,2,.追求优秀的代码风格,Use synchronous design methodology,Ensure the code is written optimally for critical paths,Pipeline（Xilinx FPGAs have abundant Registers),3.,充分利用synthesis工具和Place&Route工具参数选择,Try different optimization techniques,Add critical timing constraints in synthesis,Preserve hierarchy,Apply full and correct constraints,Use High effort,时序收敛流程,10/17/2026,31,时序收敛流程,Use embedded blocks,10/17/2026,32,Simple Coding Steps Yield 3x Performance,Use pipeline stagesmore bandwidth,Use synchronous resetbetter system control,Use Finite State Machine optimizations,Use inferable resources,Multiplexer,Shift Register LUT(SRL),Block RAM,LUT RAM,Cascade DSP,Avoid high-level constructs(loops,for example)in code,Many synthesis tool produce slow implementations,时序收敛流程,10/17/2026,33,Synthesis guidelines,Use timing constraints,Define tight but realistic individual clock constraints,Put unrelated clocks into different clock groups,Use proper options and attributes,Turn off resource sharing,Move flip-flops from IOBs closer to logic,Turn on FSM optimization,Use the,retiming,option,时序收敛流程,10/17/2026,34,时序收敛流程,Impact of Constraints,10/17/2026,35,Place&Route Guidelines,Timing constraints,Use tight,realistic constraints,Recommended options,High-effort Place&Route,By default,effort is set to,Standard,Timing-driven MAP,Multi-Pass Place&Route(MPPR),Tools to help meet timing,Floorplanning(Use the PACE and PlanAhead software tools),Physical synthesis tools,Other available options:,Incremental design,Modular design flows,时序收敛流程,10/17/2026,36,时序收敛流程,Impact of Constraints in Tools,10/17/2026,37,主要内容,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分析,时序收敛流程实现技术,时序收敛流程,FloorPlanner,和,PACE,10/17/2026,38,代码风格,使用同步设计技术,使用Xilinx-Specific代码,使用Xilinx提供的核,使用层次化设计,使用ISE产生的静态时序分析报告，找出时序关键路径，并进行优化,10/17/2026,39,主要内容,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分析,时序收敛流程实现技术,时序收敛流程,FloorPlanner,和,PACE,10/17/2026,40,使用综合工具提供的参数选项，尤其是constraint-driven技术，可以优化设计网表，提高系统性能,为综合工具指定关键路径，综合工具可以提高 工作级别，使用更深入的算法，减少关键路径延迟,综合技术,10/17/2026,41,综合工具提供许多优化选择，以获得期望的系统性能和面积要求,参考F1帮助信息,或,XST Userguide,Register Duplication,Timing-Driven Synthesis,Timing Constraint Editor,FSM Extraction,Retiming,Hierarchy Management,Schematic Viewer,Error Navigation,Cross-Probing,Physical Optimization,综合技术,10/17/2026,42,D,Q,fn1,D,Q,fn1,D,Q,fn1,High-fanout nets can be slow and hard to route,Duplicating flip-flops can fix both problems,Reduced fanout shortens net delays,Each flip-flop can fanout to a different physical region of the chip to reduce routing congestion,Design trade-offs,Gain routability and performance,Increase design area,Increase fanout of other nets,Duplicating Flip-Flops,综合技术,10/17/2026,43,Timing-Driven Synthesis,Synplify,Precision,and XST software,Timing-driven synthesis uses performance objectives to drive the optimization of the design,Based on your performance objectives,the tools will try several algorithms to attempt to meet performance while keeping the amount of resources in mind,Performance objectives are provided to the synthesis tool via timing constraints,综合技术,10/17/2026,44,实施period约束和input/output约束(.xcf文件),通常，根据期望的性能目标进行1.5X2X的过约束，综合工具会提高工作级别，有利于在实现中更容易满足时序目标,切记：,如果使用过约束，不要把这些约束传递给实现工具,使用Multi-cycle和false paths约束,使用Critical path约束，对Critical path进行优化,综合技术,Timing-Driven Synthesis,10/17/2026,45,Retiming,Synplify,Precision,and XST software,Retiming:The synthesis tool automatically tries to move register stages to balance combinatorial delay on each side of the registers,D,Q,D,Q,D,Q,Before Retiming,After Retiming,D,Q,D,Q,D,Q,综合技术,10/17/2026,46,Hierarchy Management,Synplify,Precision,and XST software,The basic settings are:,Flatten the design:Allows total combinatorial optimization across all boundaries,Maintain hierarchy:Preserves hierarchy without allowing optimization of combinatorial logic across boundaries,If you have followed the synchronous design guidelines,use the setting,-,maintain hierarchy,If you have not followed the synchronous design guidelines,use the setting -,flatten the design,Your synthesis tool may have additional settings,Refer to your synthesis documentation for details on these settings,综合技术,10/17/2026,47,Hierarchy Preservation Benefits,Easily locate problems in the code based on the hierarchical instance names contained within static timing analysis reports,Enables floorplanning and incremental design flow,The primary advantage of flattening is to optimize combinatorial logic across hierarchical boundaries,If the outputs of leaf-level blocks are registered,there is no need to flatten,综合技术,10/17/2026,48,主要内容,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分析,时序收敛流程实现技术,时序收敛流程,FloorPlanner,和,PACE,10/17/2026,49,管脚约束,管脚约束通常在设计早期就要确定下来，以保证电路板的设计同步进行,对高速设计、复杂设计和具有大量I/O管脚的设计，Xilinx推荐手工进行管脚约束,实现工具可以自动布局逻辑和管脚，但是一般来说不会是最优的,管脚约束可以指导内部数据流向,不合理的管脚布局很容易降低系统性能,合理的管脚布局需要对所设计系统和Xilinx器件结构的详细了解，如要考虑I/O bank、I/O电气标准等,时钟(单端或差分)必须约束在专用时钟管脚,注意：时钟资源数量的限制,最后使用dual-purpose管脚(如配置和DCI管脚),10/17/2026,50,根据数据流指导管脚约束,用于控制信号的I/O置于器件的顶部或底部,控制信号垂直布置,用于数据总线的I/O置于器件的左部和右部,数据流水平布置。,以上布局方法可以充分利用Xilinx器件的资源布局方式,进位链排列方式,块RAM，乘法器位置,管脚约束,10/17/2026,51,使用PACE进行管脚约束,管脚约束,10/17/2026,52,主要内容,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分析,时序收敛流程实现技术,时序收敛流程,FloorPlanner,和,PACE,10/17/2026,53,时序约束,如果实现后性能目标得到满足，则设计完成,否则，施加特定路径时序约束,施加multi-cycle，false path和关键路径约束，实现工具会优先考虑这些特定路径约束,10/17/2026,54,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分析,时序收敛流程实现技术,时序收敛流程,FloorPlanner,和,PACE,主要内容,10/17/2026,55,静态时序分析,Post-map：Map后，使用Post-map timing report确定关键路径的逻辑延迟,Post-PAR：PAR后，使用Post-PAR static timing report确定时序约束是否满足,Logic delay Vs.Routing delay：60%/40%原则,Timing Analyzer可以读取时序报告，查找关键路径，并与Floorplanner协同解决时序问题,10/17/2026,56,Report Example,静态时序分析,10/17/2026,57,Analyzing Post-Place&Route Timing,There are many factors that contribute to timing errors,including,Neglecting synchronous design rules or using incorrect HDL coding style,Poor synthesis results(too many logic levels in the path),Inaccurate or incomplete timing constraints,Poor logic mapping or placement,Each root cause has a different solution,Rewrite HDL code,Add timing constraints,Resynthesize or re-implement with different software options,Correct interpretation of timing reports can reveal the most likely cause,Therefore,the most likely solution,静态时序分析,10/17/2026,58,静态时序分析,Case1,10/17/2026,59,Poor Placement:Solutions,Increase Placement effort level(or Overall effort level),Timing-driven packing,if the placement is caused by packing unrelated logic together,Cross-probe to the Floorplanner to see what has been packed together,This option is covered in the.Advanced Implementation Options.module,PAR extra effort or MPPR options,Covered in the.Advanced Implementation Options.module,Floorplanning or Relative Location Constraints(RLOCs)if you have the skill,静态时序分析,10/17/2026,60,静态时序分析,Case2,10/17/2026,61,High Fanout:Solutions,Most likely solution is to duplicate the source of the high-fanout net,the net is the output of a flip-flop,the solution is to duplicate the flip-flop,Use manual duplication(recommended)or synthesis options,If the net is driven by combinatorial logic,locating the source of the net in the HDL code may be more difficult,Use synthesis options to duplicate the source,静态时序分析,10/17/2026,62,静态时序分析,Case3,10/17/2026,63,Too Many Logic Levels:Solutions,The implementation tools cannot do much to improve performance,The netlist must be altered to reduce the amount of logic between flip-flops,Possible solutions,Check whether the path is a multicycle path,If yes,add a multicycle path constraint,Use the retiming option during synthesis to distribute logic more evenly between flip-flops,Confirm that good coding techniques were used to build this logic(no nested if or case statements),Add a pipeline stage,静态时序分析,10/17/2026,64,时序约束的概念,时序收敛流程,时序收敛流程代码风格,时序收敛流程综合技术,时序收敛流程管脚约束,时序收敛流程时序约束,时序收敛流程静态时序分