MIPIDSIEssential(MIPI协议详细介绍).ppt

,#,MIPI DSI Essential,Table of Contents,MIPI DSI Overview,PHY Layer,D-PHY Architecture,Global Operation,Lane Management Layer,DSI Protocol Layer,2,/59,MIPI DSI Overview,Serial Interface,Low Pin Count,Reduced Power Consumption,2 Types of Data Signaling,High Speed Data Transmission-500Mbps/Lane,differential signaling,Low Power Data Transmission-10Mbps,single ended signaling,lane 0 only,Lane-Scalable,up to 4 data lanes,Packet Based Data Transmission,DSI Protocol has ECC,CRC capability-robust data transmission,Protocol Support Multiple displays(up to 4),Support All Legacy Parallel Interface Functionality,MIPI DSI Command Mode-MIPI DBI Interface(I-80 Interface),MIPI DSI Video Mode-MIPI DPI Interface(RGB Interface),3,/59,MIPI DSI Interface Physical Architecture,1 Clock Lane,unidirectional,1 to 4 Data Lanes,Lane0 is bidirectional for LP data output transmission of the driver IC,4,/59,MIPI DSI Functional Layers,Transmitter Side,8-bits,8-bits,Low Level Protocol,Data,Control,Data,Control,Add(TX)/Extract(RX)low level protocol,synchronization,ECC,CRC packet headers and footers.,Low Level Protocol,Data,Control,Data,Control,N*8-bits,TX:Distribute data to 1,2,3 or 4 lanes,RX:Assembly data from 1,2,3 or 4 to one byte stream,8-bits,8-bits,Lane Management Layer,Lane Management Layer,Receiver Side,PHY Layer,Data3,Control,PHY Layer,Control,Pixel to Byte Packing Formats,Data,Control,Pixel,Control,Pack/Unpack Pixels or Commands from/to Byte Stream,Byte to Pixel Unpacking Formats,Data,Control,Pixel,Control,Application,Pixel,Control,Application,Pixel,Control,Encode and Interpretat Data/Commands,16-,18-or 24-bit Pixels,Data2,Data1,Data0,N,*,8-bits,Data1,Data3,Data3,Data0,High Speed Unidirectional Clock,Lane 0-High Speed,bidirectional,Data,Lane 1-High Speed Unidirectional Data,Lane 2-High Speed Unidirectional Data,Lane 3-High Speed Unidirectional Data,Physical Transmission/Reception,Serializer/Deserializer,Byte Clock Generation/Recovery(DDR),per MIPI D-PHY Spec,5,/59,Video Mode Display,Display,Driver,Host,Processor,Display Panel,LCD,Display,Bus,Interface,Bus,Interface,Color,Frame,Buffer,Display Refresh,Timing,Control,Update,Frame,Buffer,6,/59,Command Mode Display,Host,Processor,Display Panel,LCD,Display,Bus,Interface,Color,Frame,Buffer,Image,Update,Data,Commands&,Image Update,Data,Bus,Interface,Display Controller,7,/59,PHY Layer,D-PHY Architecture,PHY Lane Configuration,Minimum Configuration,At least 1 Clock Lane,1 Data Lane,Reverse-direction traffic uses lane 0 only,Lane 1,2,3(if present)are unidirectional,Lane number fixed at design/manufacture(Module level),No dynamic lane configuration by host processor.,9,/59,D-PHY Lane Module(1/2),Transmission data Unit,One byte,Lane Module may contain,HS-TX,HS-RX,or both,If LP mode is used at command mode configuration,both host and peripheral must include LP Rx and LP Tx,Also CD needed if bi-directional in use,The LP-CD shall check for contention at least once before driving a new state on the line,Master and a Slave concept,10,/59,D-PHY Lane Module(2/2),Low power transmitter,High speed receiver,Low power receiver,Contention(=“collision”)detection,High speed transmitter,11,/59,Least PHY Lane Configuration-Detailed View,Data lane 0,CLK lane,*Bi-directional but,not HS reverse,*LP for bi-directional,*uni-directional,*LP for minimum,transition control,12,/59,D-PHY Signal Level,2 Types of Signal Level,HSDT,LPDT,LP VOH,-typ 1.2V,1.1V 1.3V,HS diff,-typ 200mv,140mv 270mv,HS comm,-typ 200mv,150mv 250mv,LP VOH,-typ 0V,-50mV 50mV,LP VIL:550mV,LP VIH,-typ 1.2v 0.88V 1.35V,13,/59,HS Mode-Transmitter Receiver Structure,HS Data Transmission,While HSDT is active,Termination R is enabled,R-term(ZID):100Ohm,Transmitter side,Receiver side,PCB,Conn,FPCB,0V,400mV,300mV,100mV,14,/59,HS Mode-Signaling Detailed View,300mv,100mv,200mv,100mv,200mv,V,diff,=|V,OD,|,Vdiff 200mV,Vcm 200mV Typ Condition,15,/59,HS Mode-Clock Transmission,HS Clock,DDR Clock Structure,1 Clk Period:2*UI,Clock Burst always contains an even number of transition,Clock can also run while D0 is in LP mode(especially Videomode),Ex)500Mbps,Freq:250Mhz,1Clk Period:4ns,IU=2ns,16,/59,HS Mode-Clock to Data,Data to Clock Timing Definition,90 Degree Phase Shift CLK to Data,The First bit of DSI Packet must be sent at a rising edge of HS Clk,Data Lane,Clock,Lane,17,/59,HSDT Signal in Practice,VCM=200mV nom,Vo+:typically 300mV,Vo-:typically 100mV,Vdiff(positive),18,/59,LP Signaling Detailed View,Typically 1.2V,T,LPX,-min:50ns,19,/59,LPDT Signal in Practice,2T,LPX,typically 1.2V,20,/59,DP,DN,PHY Layer,Global Operation,Data Unit Of D-PHY,Minimum Data Unit is 1 Byte,Transmitter-Byte stream-Bit stream,Receiver-Bit stream-Byte stream,HS Lane can be differential 1 or 0,LP Lane on D0 can have four state(LP+/-),LP00:Bridge,Space,LP01:HS-Rqst,Mark-0,LP10:LP-Rqst,Mart-1,LP11:Stop,22,/59,D-PHY Operation Flow Diagram,LP-11(Stop)State,The start state of every operation.,Major Three Type Modes,Escape Mode,HST,Bus Turn Around,PHY State is decided by LP state,HSDT:LP11-LP01-LP00-,HSDT-LP-11,LPDT:LP11-LP10-LP00-,Escape Mode,-LP11,In Case of Clock Lane,HST is Supported for Clock Supply,23,/59,Escape Mode Operation,Escape Mode Entry,Escape Mode Leave,Escape Mode Commands,Escape,Command,Type,Entry Command Pattern,(First bit-Last,Bit Transmitted,D1,D2,D3,D0,Low-Power,Data Transmission,Mode,1110 0001,(0 x87,LSB First),-,o,Ultra-Low Power Mode,Mode,0001 1110(0 x78),o,o,Undefined-1,Mode,1001 1111,-,-,Undefined-2,Mode,1101 1110,-,-,Reset-Trigger,Trigger,0110 0010(0 x46),-,o,Tearing Effect,Trigger,0101 1101(0 xBA),-,o,Acknowledge,Trigger,0010 0001(0 x84),-,o,Unknown-5,Trigger,1010 0000,-,-,24,/59,Escape Mode Operation-LPDT,Low Power Data Transmission,25,/59,Escape Mode Operation-Reset Trigger,Ultra Low Power State,26,/59,Escape Mode in Practice-LPDT,EME,LP11-LP10-LP00-LP01-LP00,Escape Mode Command,LPDT 1110 0001(0 x87),Data 1-1001 1100(0 x39),(Packet Header),27,/59,DP,DN,HS Mode Operation,High Speed Data Transmission Request,LP11-LP01-LP00,Clock,Data Lane:Same Entry,High Speed Clock Lane is started before Data Transmission,28,/59,HS Mode Operation-Data Lane Entry,Low Power Mode to High Speed Mode,LP11-LP01-LP00-SOT-HSDT,Synchronization Code:00011101,Data Transmission,29,/59,HS Mode Operation-Data Lane Leave,Low Power Mode to High Speed Mode,HSDT-EOT-LP11,30,/59,HS Mode Operation in Practice-LPDT to HSDT,LP01,LP00,LP11,LP Transmitter Driving,HS Transmitter Driving,HS Clock,R-term On,31,/59,DP,DN,HS Mode Operation in Practice-SOT,SOT,00011101,DATA0,32,/59,Clk,Data,Bus Turn Around,Handover Bus Possession,Host to client,client to host,When host request data from client and when host read status of client,Client must send BTA after clients data transmission,TE-signaling,Sequence(ex,Read Request to Client),Host Send Read Request to Client-Host sends BTA-Client Get Bus-Host Releases Bus-Client sends data -Client sends BTA-Host Get Bus,LP11-LP10-LP00-LP10-LP00,33,/59,Bus Turn Around in Practice,BTA,Client LPDT,Host Driving,Client Driving,34,/59,DP,DN,Lane Management Layer,Multi Lane Distribution and Merging,Distributor Function(transmit),Merger Function(receive),36,/59,Data Transmission Example-2 Lane,37,/59,Data Transmission Example-3 Lane,38,/59,DSI Protocol Layer,Packet-based Protocol,Data Flow,Image data,Signal events,Commands-Protocol Layer-Packets-,Physical layer-Packet Receive-Interpret Packet to Image data,Signal Event,Commands,Signal Event:V-sync,H-sync.,Commands:DCS Commands,Many packets can be transferred in a transmission,Packet Concatenation,Packet Types,Short Packet-4byte include ECC,Long Packet-up to 65kbytes,40,/59,Short Packet Format,ECC,Generation,-DI,-Data 0,-Data 1,ECC,41,/59,Long Packet Format,CRC,Calculation,-Data,CRC,ECC,Generation,-DI,-Word Count,ECC,42,/59,Endian Policy,Long Packet Case,LS Byte First,MS Byte Last,43,/59,Virtual Channel,Up to 4 peripherals possible with tagged command or blocks of data,using the Virtual Channel ID Field,DSI hub is needed,Not possible to connect many display to same bus,DSI,Hub,Host,Processor,Main Display Panel,LCD,Display,Bus,Interface,Bus,Interface,DSI,Out 1,Out 2,Interface,LCD,Display,Frame,Buffer,Sub-,Display,44,/59,Multiple Packets per Transmission,-With EoTp,-Without EoTp,45,/59,Data Type,Only Video Mode,Video Mode,Command Mode,Motorola Legacy operation for videomode,Protocol Specific,46,/59,Data Type,Only Video Mode,Video Mode,Command Mode,Protocol Specific,47,/59,Packets for DCS commands,DCS Short Write:write a single data byte to a peripheral,05h/15h(no parameters/one parameter),If BTA follows,ACK by display or AwER,DCS Long Write/write_LUT Command,Data Type=11 1001(39h),Used to send larger blocks of data to a display module,DI byte,a two-byte WC,an ECC byte,followed by the DCS Command Byte,a payload of length WC minus one bytes,and a two-byte checksum,DCS Read Request,No Parameters,Data Type=00 0110(06h),used to request data from a display module.,ID byte,a DCS Read command,a byte set to 00h and an ECC byte.,BTA after the command(immediately of sometime after but before next command),Display response:short or long packet,48,/59,Packets for DSI Protocol,Set Maximum Return Packet Size,Data Type=11 0111(37h),This prevents FIFO overflow for Read packet payload in processor,considering the case that,Memory read command can retrieve a numerous bytes of data.,Null Packet(Long),Data Type=00 1001(09h),This prevents the data lane(s)going back to LP-11,with less overhead to continue HS burst.,The minimum packet size is 6(4bytes PH+0 byte payload+2bytes CRC checksum).,EoTp,Data Type=00 1000(08h),Should be enabled when HSDT,An EoTp has a fixed format as follows,Data Type=DI 5:0=0b001000,Virtual Channel=DI 7:6=0b00,Payload Data 15:0=0 x0F0F,ECC 7:0=0 x01,49,/59,Packets for Videomode,Sync Event :generate video sync signal internally,V Sync Start(0 x01),V Sync End(0 x11),H Sync Start(0 x21),H Sync End(0 x31),Video Streams(Long),RGB Video Streams,50,/59,RGB Pixel Stream-16bit,24bit,24-Bit Pixel,Data Type:0 x3E,Word Count:,1H Line Pixel Length x 3,16-Bit Pixel,Data Type:0 x0E,Word Count:,1H Line Pixel Length x 2,51,/59,Video Streaming-Non Burst Operation,52,/59,Video Streaming-Burst Operation,53,/59,Reverse Transmissions,Occur on D0 after host has made BTA,Display is expected to reply data or at least reply ACK,ACK means everythings ok,Response Type,Tearing Effect(TEE),Acknowledge=ACK,Acknowledge and Error Report=AwER,Response to Read Request,BTA Must take place after display reply,Give bus back to host,54,/59,Reverse Response Data Type,55,/59,LPDT Reverse Example,11100001=LPDT,Data type 05=short write no params,00010001=0 x11=SLPOUT,ECC,BTA,Display EME,dphy table 8:ACK=00100001(0 x84),BTA back to host,56,/59,Error Detect and Reporting,Error Bit Mapping,57,/59,QnA,58,/59,