算术逻辑单元英文.pptx

,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,单击此处编辑母版标题样式,单击此处编辑母版标题样式,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,*,算术逻辑单元英文,5、1 The von Neumann puter model,The vast majority of puter systems used today are constructed on the van Neumann puter model、,A puter is viewed as a,stored program puter,、,A program is a sequence of instructions,each of which performs a basic operation、,Before execution,the program is stored in memory along with data to be manipulated、,When executed,the instructions in it are retrieved from memory,one after another,and brought into the processing unit、Decodes instruction,retrieve data,perform operation,stores result in register or memory、,Typically consists of 3 functional blocks:a central processing unit(CPU),main memory,an input/output system(I/O)、,Control unit,registers,ALU,CPU,Main,memory,Input/,Output,External,Bus,The basic organization of a stored-program puter,5、1 The von Neumann puter model,Internal Bus,5、2 Parallel fast adders,An arithmetic unit(ALU)is the heart of the CPU,The ALU usually has a binary adder,The performance of the ALU is mainly determined by its adder、,We need to design a fast adder to get rid of the excessive carry-propagation time of the ripple-carry adder、,Design of full adder,Full adder with the carry bit C,n-1,、Fn and C,n,are given as below:,Fn,XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,Cn,XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,5、2 Parallel fast adders,Design of full adder,Logic maps:,Fn,XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,Cn,XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,Formed by two half adders,F,n,:add result of X,n,、,Y,n,and C,n-1,F,n,=X,n,Y,n,C,n-1,5、2 Parallel fast adders,Design of full adder,A n bit adder can be produced by connecting n full adders,Carry is transferred serially,and F,i,is calculated when C,i-1,is ing、Time consumed is determined by number of bits、,A simple 4 bits serial full adder,5、2 Parallel fast adders,Design of a fast adder,How to improve the speed of adder?,Change the pathway of one by one carry bits,Cn,XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,+XnYnCn-,1,(Xn+Yn)Cn-,1,+XnYn,The carry of the full adder of the C,i,depends on the C,i-,1,Although n full adders work in parallel,the carry signals are generated and propagated in sequential、,The worst-case of carry propagation occurs when a carry signal propagates from C,0,to C,n,all the way along the carry propagation circuit、,5、2 Parallel fast adders,Carry look-ahead,(超前进位),It reduces significantly the carry creation time by generating the carry signals for all the bits at once directly from the input carry C,0,The nature of carry propagation,C,1,is generated as long as one of these two conditions is meeting,:,(1)Both of X,1,Y,1,are“1”,;,(2)Either of X,1,Y,1,is“1”,and C,0,is“1”,。,Then C,1,can be expressed,:,C,1,=X,1,Y,1,+(X,1,+Y,1,)C,0,5、2 Parallel fast adders,The nature of carry propagation,C,2,is generated as long as one of the following conditions is satisfied,:,(1)Both of X,2,and,Y,2,are“1”,;,(2)Either of X,2,and Y,2,is“1”,and X,1,and Y,1,are“1”,;,(3)Either of X,2,and Y,2,is“1”,and either of X,1,and Y,1,is“1”,with C,0,is“1”,Then C,2,can be expressed,:,C,2,=X,2,Y,2,+(X,2,+Y,2,)X,1,Y,1,+(X,2,+Y,2,)(X,1,+Y,1,)C,0,5、2 Parallel fast adders,The nature of carry propagation,Similarly,C,3,and C,4,can be calculated,:,C,3,=X,3,Y,3,+(X,3,+Y,3,)X,2,Y,2,+(X,3,+Y,3,)(X,2,+Y,2,)X,1,Y,1,+(X,3,+Y,3,)(X,2,+Y,2,)(X,1,+Y,1,)C,0,C,4,=X,4,Y,4,+(X,4,+Y,4,)X,3,Y,3,+(X,4,+Y,4,)(X,3,+Y,3,)X,2,Y,2,+(X,4,+Y,4,)(X,3,+Y,3,)(X,2,+Y,2,)X,1,Y,1,+(X4+Y4)(X3+Y3)(X2+Y2)(X1+Y1)C0,5、2 Parallel fast adders,大家有疑问的，可以询问和交流,可以互相讨论下，但要小声点,The nature of carry propagation,Carry propagate function P,i,and carry generate function G,i,:,G,i,=X,i,Y,i,carry generate function,P,i,=X,i,+Y,i,carry propagate function,G,i,:,when X,i,and Y,i,are“1”,no matter whether there is low-order carry bit,the current carry bit is generated、,P,i,:,when either of X,i,and Y,i,is 1,if there exist low-order carry bit,then C,i-1,is propagated to high-order carry bit,5、2 Parallel fast adders,The nature of carry propagation,Put P,1,G,1,into C,1,C,4,:,C,1,=G,1,+P,1,C,0,(,low-order bit,),C,2,=G,2,+P,2,G,1,+P,2,P,1,C,0,C,3,=G,3,+P,3,G,2,+P,3,P,2,G,1,+P,3,P,2,P,1,C,0,C,4,=G,4,+P,4,G,3,+P,4,P,3,G,2,+P,4,P,3,P,2,G,1,+P,4,P,3,P,2,P,1,C,0,5、2 Parallel fast adders,The nature of carry propagation,Since the input variables take inverted values,its output generates the inverted variables,“,NAND,”,“,NOR,”,、,“,AND-OR-NOT,”,can be readjusted as:,G,i,=X,i,Y,i,G,i,=X,i,Y,i,=X,i,+Y,i,carry generate,P,i,=X,i,+Y,i,P,i,=X,i,+Y,i,=,X,i,Y,i,carry propagate,G,i,P,i,=(X,i,+Y,i,),X,i,Y,i,=,X,i,Y,i,=P,i,C1,=,G1+P1C0,C1,=,G1+P1C0,=,G1,P1C0,=,G1,(,P1+C0),=,G1,P1+G1,C0,=,P1+G1,C0,5、2 Parallel fast adders,The nature of carry propagation,C1=P1+G1C0,C2=P2+G2P1+G2G1C0,C3=P3+G3G2+G3G2P1+G3G2G1C0,C4=P4+G4P3+G4G3P2+G4G3G2P1+G4G3G2G1C0,5、2 Parallel fast adders,5、2 Parallel fast adders,The four-bit carry look-ahead adder,5、2 Parallel fast adders,The block carry look-ahead circuit,Theoretically speaking,expression C1C4 can be expanded to higher order bits up to n-1 for n4、,However,as the bit number increases,the number of product terms and maximum number of literals in a product term in the expression would increase proportionally、,So we limit the fan-in of an AND gate or an OR gate to 5、,The maximal allowable size of a single-stage carry look-ahead circuit is 4 bits、,5、2 Parallel fast adders,The block carry look-ahead circuit,5、2 Parallel fast adders,The block carry look-ahead circuit,G=G,3,+P,3,G,2,+P,3,P,2,G,1,+P,3,P,2,P,1,G,0,P=P,3,P,2,P,1,P,0,74182,G,3,P,3,G,2,P,2,G,1,P,1,G,0,P,0,G P C,3,C,2,C,1,C,0,The result of carry generate function of 74181 G is,“,1,”,as long as one of these conditions satisfied,:,(1)Both of X,3,and Y,3,are“1”,that is G,3,=1,;,(2)Either of X,3,and Y,3,is“1”,and X,2,andY,2,are all“1”,that is P,3,G,2,=1,(3)Either of X,3,and Y,3,is“1”,and one of X,2,andY,2,is“1”,and both of X,1,and Y,1,are“1”,that is P,3,P,2,G,1,=1,;,(4)One of X,3,and Y,3,is“1”,and one of X,2,and Y,2,is“1”,and one of X,1,andY,1,is“1”,and both X,0,and Y,0,are“1”,that is P,3,P,2,P,1,G,0,=1,。,Therefore,:,G=G,3,+P,3,G,2,+P,3,P,2,G,1,+P,3,P,2,P,1,G,0,5、2 Parallel fast adders,The requirements to meet group carry propagate function of 74181 P equals 1 is,:,Either X,3,or Y,3,is“1”,Either X,2,orY,2,is“1”,Either X,1,or Y,1,is“1”,Either X,0,or Y,0,is“1”,。,Therefore,:,P=P,3,P,2,P,1,P,0,5、2 Parallel fast adders,Let C,n1,C,n2,C,n3,(C3,C7,C11)be the carrys of chip 0 to chip 1,chip 1 to chip 2 and chip 2 to chip 3、Replace G1,G2 and G3 by G,N0,G,N1,G,N2,、Replace P1,P2,P3 by P,N0,P,N1,P,N2,、Replace C,0,by Cn、Then Cn+x,Cn+y,Cn+y can be gained as follows:,5、2 Parallel fast adders,The block carry look-ahead circuit,16-bit fast adders,adder,A15A12,B15B12,74182,adder,A11A8,B11B8,adder,A7A4,B7B4,adder,A3A0,B3B0,C0,F3F0,G4 P4 C3 G3 P3 C2 G2 P2 C1 G1 P1,F7F4,F11F8,F15F12,G P,C0,5、2 Parallel fast adders,5、3 Analysis of the design of a mercial ALU chip,ALU can implement basic arithmetic operations and logical operations、,This section analyze the design process of the mercial 4-bits ALU chip SN74181、,SN74181,Logic maps and function table of 4-bits ALU,S,3,S,2,S,1,S,0,Positive logic,M=H,Logic op,M=L arithmetic operation,C,n,=1,C,n,=0,L,L,L,L,A,A,A add 1,L,L,L,H,A+B,A+B,(A+B)add 1,L,L,H,L,A,B,A+B,(A+B)add 1,L,L,H,H,“,0,”,Sub 1,“,0,”,L,H,L,L,A,B,A add(A,B),A add(A,B)add 1,L,H,L,H,B,(A,B),add,(A+B),(A,B),add,(A+B),add,1,L,H,H,L,AB,A sub B sub 1,A sub B,L,H,H,H,A,B,(A,B)sub1,A,5、3 Analysis of the design of a mercial ALU chip,SN74181,S,3,S,2,S,1,S,0,Positive logic,M=H,Logic op,M=L arithmetic operation,C,n,=1,C,n,=0,H,L,L,L,A+B,A add(A,B),A add(A,B)add 1,H,L,L,H,A B,A add B,A add B add 1,H,L,H,L,B,(A,B),add,(A+B),(A,B),add,(A+B),add,1,H,L,H,H,A,B,(A,B),sub,1,A,B,H,H,L,L,“,1,”,A,add,A,A,add,A,add,1,H,H,L,H,A+B,A,add,(A+B),A,add,(A+B),add,1,H,H,H,L,A+B,A,add,(A+B),A,add,(A+B)add,1,H,H,H,H,A,A sub 1,A,5、3 Analysis of the design of a mercial ALU chip,Logic maps and function table of 4-bits ALU,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,G,0,=A,0,+B,0,=A,0,B,0,P,0,=A,0,B,0,=A,0,+B,0,G,0,P,0,=G,0,P,0,+G,0,P,0,=(A,0,+B,0,)(A,0,+B,0,),+(A,0,B,0,)(A,0,B,0,),=0+A,0,B,0,+A,0,B,0,+0+0,=A,0,B,0,0,0,0,0,0,0,0,0,A,0,B,0,C,0,A,1,B,1,C,1,SN74181,Pins of 74181,5、3 Analysis of the design of a mercial ALU chip,16-bits ALU,Four 74181 circuits can forms 16-bits ALU,Fast carry in chip,and one by one between chips、So it would take relative long time to generate F,0,F,15,16-bits ALU formed by 4 ALU chips,5、3 Analysis of the design of a mercial ALU chip,5、3 Analysis of the design of a mercial ALU chip,16-bits ALU,Take 4 bits as a group、Using method like,“,4-bit carry look-ahead adder,”,to implement 16-bits ALU(formed by 4 ALU chips),a 16-bit fast ALU can be gained、,74181,ALU can generate,G,n,Pn,then 16-bit fast ALU can be implemented by AND OR NOT gates and 4 ALU chips,74182(Look-ahead carry extender)can be gained by implementing logic circuit of Cn1,、,Cn2,、,Cn3,16-bits fast ALU,16-bit fast ALU,74181,A15A12,B15B12,74182,74181,A11A8,B11B8,74181,A7A4,B7B4,74181,A3A0,B3B0,C0,F3F0,G4 P4 C3 G3 P3 C2 G2 P2 C1 G1 P1,F7F4,F11F8,F15F12,G P,C0,5、3 Analysis of the design of a mercial ALU chip,32-bits fast ALU,Two 16-bit 74182 and eight 74181 can form a 32-bit ALU circuit,5、3 Analysis of the design of a mercial ALU chip,64-bits fast ALU,Construct a 64-bit ALU circuit by 4 16-bit 74182 chips and 16 74181 chips、,How to make it faster?,With the increasing of integration,ALU with more bits can be integrated in one chip、For example,AM29332(32 bit ALU),produced by AMD、In pentium series processor,produced by Intel,32 bit ALU is only a part of the Chip、The basic principles are the same although the devices used are different,5、3 Analysis of the design of a mercial ALU chip,Summary,5、1 The von Neumann puter model,Typically consists of 3 functional blocks:a central processing unit(CPU),main memory,an input/output system(I/O)、,5、2 Parallel fast adders,Carry look-aheadG=X Y P=X+Y,C,1,=G,1,+P,1,C,0,(,low-order bit,),C,2,=G,2,+P,2,G,1,+P,2,P,1,C,0,C,3,=G,3,+P,3,G,2,+P,3,P,2,G,1,+P,3,P,2,P,1,C,0,C,4,=G,4,+P,4,G,3,+P,4,P,3,G,2,+P,4,P,3,P,2,G,1,+P,4,P,3,P,2,P,1,C,0,SN74182(carry look-ahead generator),5、3 Analysis of the design of a mercial ALU Chip,SN74181(4 bit ALU)16bit fast ALU 32bit fast ALU,