FPGA片上资源-FDR-FDRE-FDRS-FDRSE-说明.docx

FPGA片上资源-FDR/FDRE/FDRS/FDRSE
2010-11-23 17:47
FDR : D Flip-Flop with Synchronous Reset

Spartan-II,
Spartan-IIE
Spartan-3
Virtex,
Virtex-E
Virtex-II,
Virtex-II Pro,
Virtex-II Pro X
XC9500/XV/XL
CoolRunner
XPLA3
CoolRunner-II
Primitive
Primitive
Primitive
Primitive
Macro
Macro
FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
Macro

FDR is a single D-type flip-flop with data (D) and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdr is
begin
process (C) begin
if (C' event and C = '1') then
if (R = '1') then
Q <= '0';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (posedge C) begin
    if (R)
       Q <= 0;
    else
       Q <= D;
end
FDRE : D Flip-Flop with Clock Enable and Synchronous Reset

FDRE is a single D-type flip-flop with data (D), clock enable (CE), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low on the Low-to-High clock (C) transition. The data on the D input is loaded into the flip-flop when R is Low and CE is High during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdre is
begin
process (C) begin
if (C’ event and C = ’1’) then
if (R = ’1’) then
Q <= ’0’;
elsif (CE = ’1’) then
Q <= D;
end if;
end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (posedge C) begin
    if (R)
       Q <= 0;
    else if (CE)
       Q <= D;
end
FDRS : D Flip-Flop with Synchronous Reset and Set

FDRS is a single D-type flip-flop with data (D), synchronous set (S), and synchronous reset (R) inputs and data output (Q). The synchronous reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock (C) transition. (Reset has precedence over Set.) When S is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock transition. When R and S are Low, data on the (D) input is loaded into the flip-flop during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdrs is
begin
process (C) begin
if (C' event and C = '1') then
if (R = '1') then
     Q <= '0';
elsif (S = '1') then
Q <= '1';
else
Q <= D;
end if;
end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (posedge C) begin
    if (R)
       Q <= 0;
    else if (S)
       Q <= 1;
    else
       Q <= D;
end

FDRSE : D Flip-Flop with Synchronous Reset and Set and Clock Enable

FDRSE is a single D-type flip-flop with synchronous reset (R), synchronous set (S), and clock enable (CE) inputs and data output (Q). The reset (R) input, when High, overrides all other inputs and resets the Q output Low during the Low-to-High clock transition. (Reset has precedence over Set.) When the set (S) input is High and R is Low, the flip-flop is set, output High, during the Low-to-High clock (C) transition. Data on the D input is loaded into the flip-flop when R and S are Low and CE is High during the Low-to-High clock transition.
The flip-flop is asynchronously cleared, output Low, when power is applied.
VHDL Inference Code
architecture Behavioral of fdrse is
begin
process (C) begin
if (C’ event and C = ’1’) then
if (R = ’1’) then
Q <= ’0’;
elsif (S = ’1’) then
Q <= ’1’;
elsif (CE = ’1’) then
Q <= D;
end if;
end if;
end process;
end Behavioral;
Verilog Inference Code
always @ (posedge C) begin
    if (R)
       Q <= 0;
    else if (S)
       Q <= 1;
    else if (CE)
       Q <= D;
end