数逻教案4-1省名师优质课赛课获奖课件市赛课百校联赛优质课一等奖课件.ppt

,单击此处编辑母版标题样式,*,单击此处编辑母版文本样式,第二级,第三级,第四级,第五级,本资料仅供参考，不能作为科学依据。谢谢。本资料仅供参考，不能作为科学依据。本资料仅供参考，不能作为科学依据。谢谢。不能作为科学依据。,4.1.2全加器,4.1.3编码器,4.1.4译码器,4.1.5数值比较器,4.1.6数据选择器,4.1.7奇偶产生/校验电路,4.1,组合逻辑电路分析,4.1.1组合逻辑电路分析方法,1/39,4.1.1,组合逻辑电路分析方法,分析：,依据给定逻辑电路图，归纳出该逻辑电路逻辑功效。,组合逻辑电路分析通常采取,代数法,，普通按照以下,步骤,进行：,(1)依据给定组合逻辑电路逻辑图，从输入端开始，逐层推导出输出端逻辑函数表示式；,(2)由输出函数表示式，列出它真值表；,(3)从逻辑函数表示式或真值表，概括出给定组合逻辑电路逻辑功效。,2/39,&,&,&,&,A,B,F,图,4,-,1,-,1,异或电路逻辑图,例4,-,1分析图4,-,1,-,1所表示组合逻辑电路。,解,第一步：,依据,与非,门逻辑关系，写出各输出端表示式。,0,1,1,1,0,1,1,1,0,0,0,0,F,B,A,表,4,-,1,-,1,例,4,-,1,真值表,第二步：,列真值表。,第三步：,归纳逻辑功效。,该电路为,异或,逻辑电路。,3/39,4.1.2,全加器,&,&,&,A,B,CO,图,4,-,1,-,2,1位全加器,=1,=1,F,CI,位全加器,依据,F,及,CO,表示式，列出真值表。,按照组合逻辑电路分析步骤，首先写出各级逻辑门输出表示式：,4/39,表,4,-,1,-,2,全加器真值表,1,1,1,1,1,0,1,0,1,1,0,1,1,0,1,1,0,0,0,1,0,1,1,1,0,1,0,0,1,0,1,0,1,0,0,0,0,0,0,0,F,CO,B,A,CI,CO,CI,图,4,-,1,-,3,1位全加器逻辑符号,由真值表可见，若,A,、,B,为两个输入1位二进制数，,CI,为低位二进制数相加进位输出到本位输入，则,F,为三者之和，,CO,为三者相加向高位进位输出。,所以，该电路可完成1位二进制数全加功效，称为,全加器,。,全加器是惯用算术运算电路，图4,-,1,-,3为全加器逻辑符号。,5/39,串行进位加法器,CO,CO,B,3,A,3,CI,图,4,-,1,-,4,4,位逐位进位加法器,因为每一位相加结果，必须等到低一位进位产生以后才能建立，所以这种结构也叫做,逐位进位加法器,。,串行进位加法器特点是,结构简单,，最大缺点是,运算速度慢,。为了提升运算速度，必须减小或消除因为进位信号逐位传递所消耗时间，采取,超前进位加法器,。,B,2,A,2,B,1,A,1,B,0,A,0,CO,CI,CO,CI,CO,CI,F,3,F,2,F,1,F,0,在位全加器基础上，能够组成多位加法电路。,6/39,超前进位加法器,逻辑图,由位超前进位全加器逻辑电路可知，各位进位信号,Y,2,、,Y,3,、,Y,4,只与两个加数相关，,是并行产生,，都只需要经历一级,与非,门和一级,与或非,门延迟时间。超前进位加法器大大提升了运算速度。,CO,CI,3,0,Q,3,0,P,3,0,图,4,-,1,-,6,4,位全加器逻辑符号,位超前进位全加器集成电路有：CT54 283/CT74 283、CT54 S 283/CT74 S 283、CT54 LS 283/CT74 LS 283、CC4008等。,7/39,4.1.3,编码器,编码,：就是在选定一系列二进制数码中，赋予每个二进制数码以某一固定含义。能完成编码功效电路称为,编码器,。,X/Y,图,4,-,1,-,7,编码器通用逻辑符号,在电子设备中将字符变换成二进制数，叫做,字符编码,。,用二进制数码表示十进制数，叫做,二十进制编码,。,能识别输入（请求编码）信号优先级别，并进行编码逻辑部件称为,优先编码器,。,依据编码概念，编码器输入端子数,N,和输出端子数,n,应该满足关系式：,N,2,n,。,概念,8/39,优先编码器,逻辑图,若不考虑附加电路,ST,、,Y,S,、,Y,EX,，则电路输出方程为：,依据输出方程列写真值表。,真值表,由真值表可见，若,IN,7,=0，不论其它输入端数据为0或1，输出,Y,2,Y,1,Y,0,=000，用二进制反码形式表示数“,”。这说明,IN,7,优先级别最高，,IN,6,次之，依这类推。,9/39,IN,0,IN,1,IN,2,IN,3,IN,4,IN,5,IN,6,IN,7,ST,0/Z10,1/Z11,2/Z12,3/Z13,4/Z14,5/Z15,6/Z16,7/Z17,10,11,12,13,14,15,16,17,HPRI/BIN,1a,ENa,Y,0,Y,1,Y,2,2a,4a,a,Y,EX,Y,S,18,1,图,4,-,1,-,9,8线,-3线,优先编码器,CT54148/CT74148,逻辑符号,惯用中规模优先编码器,8线,-,3线优先编码器：,CT54148/CT74148,CT54LS148/CT74LS148,CC4532,10线,-,4线优先编码器：,CT54147/CT74147,CT54LS147/CT74LS147,CC40147,键控,8421BCD,码编码器,10/39,0,1,2,3,4,5,6,7,EN,HPRI/BIN,低位片,ST,Y,S,Y,0,Y,1,Y,2,Y,EX,0,1,2,3,4,5,6,7,EN,HPRI/BIN,高位片,ST,Y,S,Y,0,Y,1,Y,2,Y,EX,&,&,&,Y,0,Y,1,Y,2,Y,3,&,Y,EX,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,图,4,-,1,-,10,8,线,-,3,线扩展为,16,线,-4线,优先编码器,编码器功效扩展,用两片8线,-,3线优先编码器扩展成为16线,-,4线优先编码器。,若高位片输入中有低电平，则因为对应,Y,S,=1，使得低位片输出被封锁，结果取决于高位片输出。反之则取决于低位片输出。,11/39,4.1.4,译码器,概念,：,译码,是编码逆过程，将输入每个二进制代码赋予含义“翻译”过来，并给出对应输出信号。含有译码功效逻辑部件称为,译码器,。,2线,-,4线译码器,依据译码概念，译码器输出端子数,N,和输入端子数,n,之间应该满足关系式：,N,2,n,。,&,&,&,&,1,1,1,1,1,.,Y,0,ST,Y,1,Y,2,Y,3,A,0,A,1,图,4,-,1,-,11,译码器逻辑图,写输出表示式：,演示,12/39,ST,A,1,A,0,Y,3,Y,2,Y,1,Y,0,1,1,1,1,1,0,0,0,1,1,1,0,0,0,1,1,1,0,1,0,1,0,1,0,1,1,0,1,1,0,1,1,1,表,4,-,1,-,4,2,线,-,4,线译码器真值表,BIN/OCT,Y,0,ST,Y,1,Y,2,Y,3,A,0,A,1,1,2,EN,0,1,2,3,图,4,-,1,-,12,2,线,-,4,线译码器逻辑符号,由输出表示式列真值表。,1高电平，0低电平，任意，低电平有效。,由真值表可见，在选通端,ST,（低电平有效）为0时，对应译码地址输入端,A,1,、,A,0,每一组代码输入，都能译成在对应输出端输出低电平0。,在译码过程中，任何时刻只有一个输出端为有效电平，且其余输出端都为相反电平。,13/39,3线,-,8线译码器,BIN/OCT,Y,0,ST,B,Y,1,Y,2,Y,3,A,0,A,1,1,2,EN,0,1,2,3,图,4,-,1,-,14,3,线,-,8,线译码器逻辑符号,4,5,6,7,Y,4,Y,5,Y,6,Y,7,ST,C,ST,A,A,2,4,&,ST,A,ST,B,+,ST,C,A,2,A,1,A,0,Y,0,Y,1,Y,2,Y,3,Y,4,Y,5,Y,6,Y,7,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,0,0,0,0,0,1,1,1,1,1,1,1,1,0,0,0,1,1,0,1,1,1,1,1,1,1,0,0,1,0,1,1,0,1,1,1,1,1,1,0,0,1,1,1,1,1,0,1,1,1,1,1,0,1,0,0,1,1,1,1,0,1,1,1,1,0,1,0,1,1,1,1,1,1,0,1,1,1,0,1,1,0,1,1,1,1,1,1,0,1,1,0,1,1,1,1,1,1,1,1,1,1,0,表,4,-,1,-,6,3,线,-,8,线译码器真值表,选通信号，高电平有效。,选通信号，低电平有效。,14/39,4线,-,10线译码器（二十进制译码器）,BCD/DEC,Y,0,Y,1,Y,2,Y,3,A,0,A,1,1,2,0,1,2,3,图,4,-,1,-,15,4,线,-,10,线译码器逻辑符号,4,5,6,7,Y,4,Y,5,Y,6,Y,7,A,2,4,A,3,A,2,A,1,A,0,Y,0,Y,1,Y,2,Y,3,Y,4,Y,5,Y,6,Y,7,Y,8,Y,9,0,0,0,0,0,1,1,1,1,1,1,1,1,1,0,0,0,1,1,0,1,1,1,1,1,1,1,1,0,0,1,0,1,1,0,1,1,1,1,1,1,1,0,0,1,1,1,1,1,0,1,1,1,1,1,1,0,1,0,0,1,1,1,1,0,1,1,1,1,1,0,1,0,1,1,1,1,1,1,0,1,1,1,1,0,1,1,0,1,1,1,1,1,1,0,1,1,1,0,1,1,1,1,1,1,1,1,1,1,0,1,1,1,0,0,0,1,1,1,1,1,1,1,1,0,1,1,0,0,1,1,1,1,1,1,1,1,1,1,0,1,0,1,0,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,0,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,表,4,-,1,-,7,4,线,-,10,线译码器真值表,A,3,8,8,9,Y,8,Y,9,无效输入状态。,演示,15/39,译码器功效扩展,ST,BIN/OCT,1,2,EN,图,4,-,1,-,13,2,线,-,4,线译码器扩展成,3,线,-,8,线译码器,A,0,3,2,1,0,Y,4,Y,5,Y,6,Y,7,Y,0,Y,1,Y,2,Y,3,BIN/OCT,1,2,EN,3,2,1,0,1,A,1,A,2,ST,1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,0,1,0,1,1,1,1,1,1,1,0,1,1,1,0,1,1,1,1,1,0,1,1,1,0,0,1,1,1,1,0,1,1,1,1,1,1,0,1,1,0,1,1,1,1,1,0,1,0,1,0,1,1,1,1,1,1,1,0,0,0,1,1,1,1,1,1,1,0,0,0,Y,0,Y,1,Y,2,Y,3,Y,4,Y,5,Y,6,Y,7,A,0,A,1,A,2,表,4,-,1,-,5,图,4,-,1,-,13,所表示电路功效表,注意：,新增输入端普通作为最高位输入端，这么能够使得输出端排列有序。,用,2,线,-,4,线译码器扩展成,3,线,-,8,线译码器。,16/39,用,2,线,-,4,线和,4,线,-,10,线译码器扩展成,5,线,-,32,线译码器。,D,BIN/OCT,1,2,EN,图,4,-,1,-,16,利用,BIN/OCT和BCD/DEC,组成,5,线,-,32,线译码器,0,1,2,3,BCD/DEC,A,1,0,1,2,3,A,0,A,3,A,2,4,5,6,7,8,9,Y,0,Y,7,BCD/DEC,A,1,0,1,2,3,A,0,A,3,A,2,4,5,6,7,8,9,Y,8,Y,15,BCD/DEC,A,1,0,1,2,3,A,0,A,3,A,2,4,5,6,7,8,9,Y,16,Y,23,BCD/DEC,A,1,0,1,2,3,A,0,A,3,A,2,4,5,6,7,8,9,Y,24,Y,31,A,1,A,0,A,3,A,2,A,4,片产生4个片选通信号，每次选中一片,4,线,-,10,线译码器，从8个输出端中输出一个有效信号，其余各片输出均为1。,17/39,译码器用作数据分配器,DMUX,0,1,EN,G,0,3,0,1,2,3,Y,0,Y,1,Y,2,Y,3,A,0,A,1,D,图,4,-,1,-,17,数据分配器逻辑符号,依据译码器输出表示式有：,这说明，经过改变地址码输入端二进制代码，能够将选通输入端数据分配到不一样输出端，从而实现数据分配逻辑功效。,若采取CT74S138，从,ST,A,端输入数据（其它选通输入端接有效电平），可将数据以,相反极性,分配到输出端。,18/39,a,b,c,d,e,f,g,A,0,A,1,A,2,A,3,BIN/7.SEG,&,1,a,b,c,d,e,f,g,LT,BI,/,RBO,RBI,图,4,-,1,-,19,七段显示译码器逻辑符号,七段显示译码器,图,4,-,1,-,18,七段字形,功效：,将输入二十进制代码转换成十进制数码对应各段驱动信号。,LT,为灯测试输入，低电平有效。,BI,/,RBO,为消隐（熄灭状态）输入和灭零输出端口，低电平有效。,RBI,为灭零输入，低电平有效，使得显示器只显示非零数据。,19/39,将,BI,/,RBO,与,RBI,配合使用，可实现多位数码显示灭零控制和数码闪烁效果。,十进制或功效,输入,BI,RBO,输出,字形,LT,RBI,A,3,A,2,A,1,A,0,Y,a,Y,b,Y,c,Y,d,Y,e,Y,f,Y,g,0,1,1,0,0,0,0,1,1,1,1,1,1,1,0,1,1,0,0,0,1,1,0,1,1,0,0,0,0,15,1,1,1,1,1,1,0,0,0,0,0,0,0,消隐,0,0,0,0,0,0,0,0,脉冲消隐,1,0,0,0,0,0,0,0,0,0,0,0,0,0,灯测试,0,1,1,1,1,1,1,1,1,表,4,-,1,-,8,七段显示译码器功效表,20/39,概念,：能完成比较两个数字大小或是否相等各种逻辑功效电路统称为数值比较器。,4.1.5,数值比较器,位数值比较器,COMP,图,4,-,1,-,22,数值比较器通用逻辑符号,图,4,-,1,-,23 1,位数值比较器,&,A,&,&,1,&,B,F,AB,F,A B,F,A B,&,依据电路写表示式：,依据表示式列写数值比较器真值表：,21/39,表,4,-,1,-,9,图,4,-,1,-,23,所表示电路真值表,输 入,输 出,A,B,F,AB,F,A=B,F,AB,0,0,0,1,0,0,1,0,0,1,1,0,1,0,0,1,1,0,1,0,集成位数值比较器,多位数值比较器是由高位开始比较，逐位进行。对于集成数值比较器，设置有级联信号输入端，接收来自低位比较器输出结果。若比较器各位比较结果都相等，最终止果取决于级联信号输入。,22/39,图,4,-,1,-,25,4,位数值比较器逻辑符号,COMP,A,0,A,1,A,2,A,B,A,B,A,B,0,3,P,F,AB,F,AB,A,3,B,0,B,1,B,2,0,3,Q,B,3,PQ,PQ,PQ,F,AB,来自低位片比较结果。,在单独使用或作为最低位片使用时，为了不影响比较结果，低位片级联输入,A,B,、,A,B,A,B,F,A,B,3,1,0,0,A,3,B,2,1,0,0,A,3,=,B,3,A,2,B,1,1,0,0,A,3,=,B,3,A,2,=,B,2,A,1,B,0,1,0,0,A,3,=,B,3,A,2,=,B,2,A,1,=,B,1,A,0,B,0,0,1,0,A,3,=,B,3,A,2,=,B,2,A,1,=,B,1,A,0,=,B,0,1,0,0,1,0,0,A,3,=,B,3,A,2,=,B,2,A,1,=,B,1,A,0,=,B,0,0,1,0,0,1,0,A,3,=,B,3,A,2,=,B,2,A,1,=,B,1,A,0,=,B,0,0,0,1,0,0,1,表,4,-,1,-,10 4,位数值比较器真值表,24/39,F,AB,F,AB,F,AB,COMP 高位片,A,4,A,5,A,6,0,3,P,A,7,Q,PQ,PQ,PQ,0,3,B,4,B,5,B,6,B,7,COMP 低位片,A,0,A,1,A,2,0,3,P,A,3,Q,PQ,PQ,PQ,0,3,B,0,B,1,B,2,B,3,1,图,4,-,1,-,26 4,位数值比较器扩展成,8,位数值比较器,数值比较器位数扩展,(1)级联扩展,由图可见，低位比较结果作为高位条件。级联扩展法结构简单，但运算速度低。,25/39,(2)并联扩展,COMP,0,0,3,P,Q,PQ,PQ,0,3,COMP,4,A,3,PQ,PQ,B,3,0,0,1,A,2,B,2,A,1,B,1,A,0,B,0,P,Q,COMP,1,0,3,P,Q,PQ,PQ,0,3,COMP,2,0,3,P,Q,PQ,PQ,0,3,COMP,3,0,3,P,Q,PQ,PQ,0,3,A,0,A,3,B,0,B,3,A,4,A,7,B,4,B,7,A,8,A,11,B,8,B,11,A,12,A,15,B,12,B,15,0,0,1,0,0,1,0,0,1,0,0,1,图,4,-,1,-,26,补,并联方式扩展数值比较器位数,并联扩展采取两级比较法，各组比较是并行进行，所以运算速度比级联扩展快。,26/39,功效描述,：选择多个输入通道中任意一路信号传送到输出端，作为输出信号。,特点,：在某一时刻，,N,个输入端中只允许有个输入信号被选择作为输出信号；输入信号选择是经过,数据选择端,（地址端）二进制代码来进行。显然，数据选择端子数目,n,应该满足,N,2,n,关系。,4.1.6,数据选择器,MUX,图,4,-,1,-,27,数据选择器通用逻辑符号,回顾与联络,：数据选择器与前面介绍数据分配器相比较，在对数据处理方面含有相反作用。,27/39,双,4,选,1,数据选择器,逻辑图,依据逻辑图及传输门工作特点，写出函数表示式：,可见，经过,A,1,A,0,种组合，能够从,D,3,D,0,路输入数据中选择路送到输出端，从而实现了数据选择功效。,D,23,D,13,1,1,0,D,22,D,12,0,1,0,D,21,D,11,1,0,0,D,20,D,10,0,0,0,0,0,1,Y,0,Y,1,A,0,A,1,ST,1,(,ST,2,),表,4,-,1,-,11,双,4,选,1,数据选择器,真值表,28/39,8,选,1,数据选择器,CT54S151/CT74S151,MUX,ST,A,0,A,1,A,2,D,0,D,1,D,2,D,3,D,4,D,5,D,6,D,7,0,2,0,1,2,3,4,5,6,7,G,0,7,Y,W,图,4,-,1,-,30 8,选,1,数据选择器逻辑符号,EN,ST,A,2,A,1,A,0,Y,W,1,0,1,0,0,0,0,D,0,D,0,0,0,0,1,D,1,D,1,0,0,1,0,D,2,D,2,0,0,1,1,D,3,D,3,0,1,0,0,D,4,D,4,0,1,0,1,D,5,D,5,0,1,1,0,D,6,D,6,0,1,1,1,D,7,D,7,表,4,-,1,-,12 8,选,1,数据选择器真值表,CT54S151/CT74S151是互补输出8选1数据选择器。,演示,29/39,MUX,A,0,A,1,D,0,D,1,D,2,D,3,0,1,0,1,2,3,G,0,3,0,1,2,3,EN,EN,D,4,D,5,D,6,D,7,A,2,1,Y,1,数据选择器功效扩展,图,4,-,1,-,31,补 由,CT74153,双,4,选,1,数据选择器组成,8,选,1,数据选择器,(1)双4选1数据选择器扩展为8选1数据选择器,合理地利用数据选择器选通端，能够实现功效扩展。,30/39,EN,0 1 2 3,1,G,0,3,MUX,Y,0,Y,(2)8选1数据选择器扩展为32选1数据选择器,EN,0 7,2,G,0,7,MUX,Y,0,A,0,A,1,A,2,A,3,A,4,EN,0 7,2,G,0,7,MUX,Y,0,EN,0 7,2,G,0,7,MUX,Y,0,EN,0 7,D,0,D,7,D,8,D,15,D,16,D,23,D,24,D,31,2,G,0,7,MUX,Y,0,图,4,-,1,-,31,8,选,1,扩展成,32,选,1,一个结构,32选4,4 选 1,31/39,1,2,EN,0 1 2 3,BIN/OCT,A,0,A,1,A,2,A,3,A,4,EN,0 7,2,0,G,0,7,MUX,Y,D,0,D,7,D,8,D,15,D,16,D,23,D,24,D,32,1,Y,EN,0 7,2,0,G,0,7,MUX,Y,EN,0 7,2,0,G,0,7,MUX,Y,EN,0 7,2,0,G,0,7,MUX,Y,图,4,-,1,-,31,补,8,选,1,扩展成,32,选,1,一个结构,4片选1,8 选 1,32/39,奇偶校验,：,在信息码之后，加一位校验码位，使码组中1码元个数为奇数或偶数。若有一位由变为或由变为，则码组中码元数奇偶性不符原先约定，因而能检测出有,一位,差错。,有奇偶校验能力及能产生校验奇偶码电路称为,奇偶检验/产生电路,。,4.1.7,奇偶产生/校验电路,2k+1,2k,(a),奇校验单元,(b),偶校验单元,图,4,-,1,-,32,奇偶校验单元逻辑符号,概念,33/39,表,4,-,1,-,13,9,位奇偶产生器/校验器真值表,F,EV,F,OD,G,3,(EVEN),G,4,(ODD),EVEN,ODD,A,B,C,D,E,F,G,H,2k,=,=,若输入中个数为偶数，则,若输入中个数为奇数，则,4,3,3,4,输 入,输 出,AH中1数目,EVEN,ODD,F,EV,F,OD,偶数,1,0,1,0,偶数,0,1,0,1,奇数,1,0,0,1,奇数,0,1,1,0,1,1,0,0,0,0,1,1,图,4,-,1,-,33,9,位奇偶产生器/校验器,(CT54180/CT74180),逻辑符号,9位奇偶产生器/校验器,34/39,奇偶校验器应用,EVEN,ODD,A,B,C,D,E,F,G,H,2k+1,EVEN,ODD,A,B,C,D,E,F,G,H,2k+1,1,D,0,D,7,D,0,D,7,F,OD,F,OD,F,EV,1,图,4,-,1,-,34,奇偶校验系统,奇数产生器,。若输入中有奇数个1，则,F,OD,=0；反之,F,OD,=1。,奇数校验器,。若传输正确，则,F,OD,=1，,F,EV,=0；不然相反。,35/39,1,&,&,&,&,1,1,&,&,&,1,1,&,&,1,1,&,1,&,&,&,&,1,=1,=1,=1,=1,1,1,&,1,&,1,&,1,&,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,X,1,Y,1,X,2,Y,2,X,3,Y,3,X,4,Y,4,F,1,(4),F,2,(1),F,3,(13),F,4,(10),CO,(9),(7),CI,1,(5),A,1,(6),B,1,(3),A,2,(2),B,2,(14),A,3,(15),B,3,(12),A,4,(11),B,4,图,4,-,1,-,5,4,位超前进位全加器,.,.,.,.,.,.,.,.,返回,36/39,1,&,1,&,&,&,&,1,&,&,&,&,1,&,&,&,&,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,1,1,.,1,1,.,1,1,.,1,1,.,1,1,1,1,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,.,Y,S,(15),Y,EX,(14),Y,0,(9),Y,1,(7),Y,2,(6),(5),ST,(4),IN,7,(3),IN,6,(2),IN,5,(1),IN,4,(13),IN,3,(12),IN,2,(11),IN,1,(10),IN,0,图,4,-,1,-,8,优先编码器逻辑图,返回,37/39,输入,输出,ST,IN,0,IN,1,IN,2,IN,3,IN,4,IN,5,IN,6,IN,7,Y,2,Y,1,Y,0,Y,EX,Y,S,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,1,0,0,1,0,0,1,0,1,0,0,1,1,0,1,0,0,1,0,0,1,1,1,0,1,1,0,1,0,0,1,1,1,1,1,0,0,0,1,0,0,1,1,1,1,1,1,0,1,0,1,0,0,1,1,1,1,1,1,1,1,0,0,1,0,0,1,1,1,1,1,1,1,1,1,1,0,1,1高电平，0低电平，,任意，输入低电平有效。,表,4,-,1,-,3,8线,-,3线优先编码器真值表,返回,选通输入端，低电平有效。,选通输出端，高电平有效。,扩展端，低电平有效。,38/39,1,TG1,1,TG2,TG5,1,TG3,1,TG4,TG6,1,1,1,1,1,A,1,A,0,D,10,D,11,D,12,D,13,ST,1,Y,1,1,TG1,1,TG2,TG5,1,TG3,1,TG6,1,D,20,D,21,D,22,D,23,ST,2,Y,2,TG4,图,4,-,1,-2,8,双,4,选,1,数据选择器,返回,MUX,ST,1,A,0,A,1,D,10,D,11,D,12,D,13,0,1,0,1,2,3,G,0,3,Y,1,Y,2,EN,39/39,